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    • 92. 发明授权
    • Power management circuit and methodology for battery-powered systems
    • 电池供电系统的电源管理电路和方法
    • US07548041B2
    • 2009-06-16
    • US11024473
    • 2004-12-30
    • Roger A. ZemkeDavid B. Bell
    • Roger A. ZemkeDavid B. Bell
    • H02J7/00
    • H02J7/0068
    • A power management system including a battery-powered application, in which an input current is supplied by a source of current that may be a current-constrained source, such as a USB port, to a battery for charging the battery and to an application load. Battery charging current is supplied to the battery for a period of time based on magnitude of battery charging current, so that charging current of lesser magnitude is applied to the battery for a greater period of time. In accord with one implementation, battery charging current is determined by monitoring the difference between a programmed charging current, dependent on battery type, and magnitude of current used by the load. Change of battery charging current due to voltage mode charging, when charge current begins to drop as the battery approaches full charge, is detected, and in response, the charging period is set to a fixed charging period based on the battery.
    • 一种电源管理系统,包括电池供电的应用,其中输入电流由可能是电流受限的源(例如USB端口)的电流源提供给用于对电池充电的电池和应用负载 。 基于电池充电电流的大小,电池充电电流被提供给电池一段时间,使得较小的充电电流被更长时间地应用于电池。 根据一个实施方案,通过监视编程的充电电流(取决于电池类型)和负载所使用的电流的大小之间的差异来确定电池充电电流。 检测到当电池接近满充电时充电电流开始下降时由于电压模式充电而导致的电池充电电流的变化,作为响应,基于电池将充电期间设定为固定的充电期间。
    • 93. 发明授权
    • Level shift delay equalization circuit and methodology
    • 电平移位延迟均衡电路和方法
    • US07545173B2
    • 2009-06-09
    • US11315146
    • 2005-12-23
    • Burt Lee Price
    • Burt Lee Price
    • H03K19/0175
    • H03K19/0013H03K19/00323
    • Transition delays in a level shift circuit are equalized by generating a first signal related to the state of the input signal, a second signal inversely related to the state of the input signal, and a third signal that is reciprocal to the second signal. Upon transition of the input signal from a high state to a low state, the third signal is selected for controlling the output until the first signal attains a high state. The first signal is selected for controlling the output when it has reached a high state after the input signal transition. The first signal remains selected upon transition of the input signal from a high state to a low state. Thus, output delays are equalized and reduced to the shortest delay.
    • 通过产生与输入信号的状态相关的第一信号,与输入信号的状态相反的第二信号和与第二信号相反的第三信号,使电平移位电路中的转换延迟相等。 在将输入信号从高状态转换到低状态时,选择第三信号以控制输出,直到第一信号达到高状态。 选择第一个信号以在输入信号转换后达到高电平状态时控制输出。 当输入信号从高状态转变到低状态时,第一信号保持选择。 因此,输出延迟被均衡并且减小到最短的延迟。
    • 94. 发明申请
    • METHOD FOR CLAMPING A SEMICONDUCTOR REGION AT OR NEAR GROUND
    • 用于夹紧或接近半导体区域的方法
    • US20090121770A1
    • 2009-05-14
    • US12033600
    • 2008-02-19
    • Samuel Patrick RankinRobert C. Dobkin
    • Samuel Patrick RankinRobert C. Dobkin
    • H03K5/08
    • G05F3/265H01L27/0248
    • A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio.
    • 钳位电路钳位由n型半导体区域接收的电压,而不使用肖特基晶体管。 钳位电路包括电流镜以及第一和第二双极晶体管。 电流镜接收第一电流并提供响应的第二电流。 第一电流由第一双极晶体管接收,第二电流由第二双极晶体管接收。 第一和第二双极晶体管的基极 - 发射极结电压之间的差异部分地限定了n型区域被钳位的电压。 为了正确启动电路,从设置在电流反射镜中的晶体管的基极/栅极端子取出电流。 该电路可选地包括一对交叉耦合的晶体管,以减少输出阻抗并提高电源抑制比。
    • 95. 发明授权
    • Asymmetric minor hysteresis loop model and circuit simulator including the same
    • 非对称小磁滞回线模型和电路模拟器包括相同
    • US07502723B1
    • 2009-03-10
    • US11216008
    • 2005-09-01
    • Michael Thomas Engelhardt
    • Michael Thomas Engelhardt
    • G06F7/60G06F17/50
    • G06F17/5036
    • The present disclosure relates to simulating inductors wound on a ferromagnetic core as the magnetic material saturates. In one application, the present disclosure is advantageously used to model the asymmetric minor hysteresis loops commonly traversed by the output inductor of a switch mode power supply. An advantage of the subject matter of the disclosure is that it allows practical nonlinear inductors to be modeled in a computationally lightweight manner without conventional non-physical behavior under asymmetric minor hysteresis loop traversals. The disclosure is also conveniently applicable to practical ferromagnetic core materials because, in one particular implementation, the input parameters to the model are the core's coercive force (Hc), remnant magnetization flux density (Br), and saturation flux density (Bs).
    • 本公开涉及当磁性材料饱和时模拟缠绕在铁磁芯上的电感器。 在一个应用中,本公开有利地用于对通常由开关模式电源的输出电感器穿过的非对称次级磁滞回线进行建模。 本公开的主题的优点在于,其允许在非对称的小磁滞回线遍历下,以计算轻量级的方式对实际的非线性电感进行建模而无需常规的非物理行为。 本发明也适用于实际的铁磁芯材料,因为在一个具体实施方式中,模型的输入参数是核心的矫顽力(Hc),剩余磁通密度(Br)和饱和磁通密度(Bs)。
    • 98. 发明授权
    • Spread spectrum modulation of a clock signal for reduction of electromagnetic interference
    • 扩展时钟信号的频谱调制,以减少电磁干扰
    • US07417509B2
    • 2008-08-26
    • US11366590
    • 2006-03-03
    • Michael Alfred Kultgen
    • Michael Alfred Kultgen
    • H03L7/00
    • H04B15/04
    • A spread spectrum frequency modulated oscillator circuit usable as a clock comprises a reference component such as a resistor, a voltage controlled oscillator and a first circuit coupled to the reference component and voltage controlled oscillator and configured to supply a first control signal to the oscillator to cause the oscillator to oscillate at a frequency corresponding to a value of the reference component. A second circuit configured to supply a random signal to the oscillator causes the frequency of the oscillator to dither. To cause the oscillator to exhibit random frequency modulation that is fast enough to reduce EMI but not too fast for controlled devices such as switching regulators to track, the oscillator includes a third circuit configured to control (1) a rate of change of the oscillator frequency such that the rate of change is a fixed percentage of the oscillator frequency, and (2) an amount of frequency change in the oscillator frequency such that the amount of frequency change is a fixed percentage of the oscillator frequency.
    • 可用作时钟的扩谱频率调制振荡器电路包括诸如电阻器,压控振荡器和耦合到参考部件和压控振荡器的第一电路的参考部件,并且被配置为向振荡器提供第一控制信号以引起 振荡器以对应于参考分量的值的频率振荡。 被配置为向振荡器提供随机信号的第二电路导致振荡器的频率抖动。 为了使振荡器呈现出足够快的随机频率调制以减少EMI,但对于诸如开关稳压器之间的受控设备来说不太快,振荡器包括被配置为控制(1)振荡器频率的变化率的第三电路 使得变化率是振荡器频率的固定百分比,和(2)振荡器频率的频率变化量,使得频率变化量是振荡器频率的固定百分比。
    • 99. 发明授权
    • Gradient insensitive split-core digital to analog converter
    • 梯度不敏感的分裂芯数转换器
    • US07414561B1
    • 2008-08-19
    • US11704441
    • 2007-02-08
    • James Lee Brubaker
    • James Lee Brubaker
    • H03M1/68
    • H03M1/0682H03M1/682H03M1/747H03M1/765
    • Digital to analog converter circuits and methods are provided for producing an analog output voltage indicative of a digital input signal with at least partial insensitivity to error gradients. Described are split-core resistive elements, which include a plurality of one-dimensional or multi-dimensional resistive strings, that may be used to reduce or substantially eliminate the effects that error gradients have on the linearity of the analog output voltages of a resistive string or interpolating amplifier DACs. The resistor strings that make up the split-core resistive elements are configured in such a manner that combining respective output voltages from each of the resistor strings results in an analog output voltage that is at least partially insensitive to the effects of error gradients.
    • 提供数模转换器电路和方法用于产生表示对错误梯度至少部分不敏感的数字输入信号的模拟输出电压。 描述的是分离电阻元件,其包括多个一维或多维电阻串,其可用于减少或基本上消除误差梯度对电阻串的模拟输出电压的线性的影响 或内插放大器DAC。 构成分离电阻元件的电阻串以这样的方式配置,即组合来自每个电阻器串的各个输出电压导致对误差梯度的影响至少部分不敏感的模拟输出电压。