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91. 发明申请

US20120276744A1 Patterning Method for High Density Pillar Structures 有权
标题翻译：高密度柱结构图案化方法
公开(公告)号：US20120276744A1
公开(公告)日：2012-11-01
申请号：US13463260
申请日：2012-05-03
申请人： Natalie Nguyen , Paul Wai Kie Poon , Steven J. Radigan , Michael Konevecki , Yung-Tin Chen , Raghuveer Makala , Vance Dunton
发明人： Natalie Nguyen , Paul Wai Kie Poon , Steven J. Radigan , Michael Konevecki , Yung-Tin Chen , Raghuveer Makala , Vance Dunton
IPC分类号： H01L21/302
CPC分类号： H01L21/0274 , H01L21/0337 , H01L27/1021 , Y10S438/947 , Y10S438/948 , Y10S438/949
摘要： A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.
摘要翻译：制造器件的方法包括在牺牲层上形成第一光致抗蚀剂层，图案化第一光致抗蚀剂层以形成第一光致抗蚀剂特征，使得第一光致抗蚀剂特征不溶于溶剂，在第一光致抗蚀剂特征上形成第二光致抗蚀剂层，第二光致抗蚀剂层以形成第二光致抗蚀剂特征，在第一和第二光致抗蚀剂特征上形成间隔层，蚀刻间隔层以形成间隔物特征并暴露第一和第二光致抗蚀剂特征，在间隔物特征之间形成第三光致抗蚀剂特征，去除间隔物特征，并且使用第一，第二和第三光致抗蚀剂特征作为掩模来图案化牺牲层以形成牺牲特征。

92. 发明授权

US08283706B2 Optimization of critical dimensions and pitch of patterned features in and above a substrate 有权
标题翻译：优化衬底中和图案上的图案特征的临界尺寸和间距
公开(公告)号：US08283706B2
公开(公告)日：2012-10-09
申请号：US12136766
申请日：2008-06-10
申请人： James M. Cleeves , Roy E. Scheuerlein
发明人： James M. Cleeves , Roy E. Scheuerlein
IPC分类号： H01L29/80
CPC分类号： H01L27/105 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
摘要翻译：在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。存储器阵列的一个级别包括例如平行轨道和扇出区域。希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术以在轨道，并且在不太关键的扇出区域更放松。

93. 发明授权

US08270210B2 Pulse reset for non-volatile storage 有权
标题翻译：用于非易失性存储的脉冲复位
公开(公告)号：US08270210B2
公开(公告)日：2012-09-18
申请号：US13154795
申请日：2011-06-07
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C7/12 , G11C7/22 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/32 , G11C2213/34 , G11C2213/71
摘要： A non-volatile storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits to SET and RESET the resistance-switching elements. The circuits that RESET the resistance-switching elements provide a pulse to the memory cells that is large enough in magnitude to SET and RESET the memory cells, and long enough to potentially RESET the memory cell but not long enough to SET the memory cells.
摘要翻译：非易失性存储系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储单元的三维存储器阵列（衬底上方），以及用于设置和复位电阻切换元素。复位电阻切换元件的电路向存储器单元提供足够大的脉冲以设置和复位存储器单元，并且足够长以潜在地重置存储器单元，但不足以设置存储器单元。

94. 发明申请

US20120223380A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 有权
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20120223380A1
公开(公告)日：2012-09-06
申请号：US13468731
申请日：2012-05-10
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L29/788 , H01L21/336 , H01L29/792
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

95. 发明授权

US08241969B2 Patterning method for high density pillar structures 有权
公开(公告)号：US08241969B2
公开(公告)日：2012-08-14
申请号：US13216688
申请日：2011-08-24
申请人： Natalie Nguyen , Paul Wai Kie Poon , Steven J. Radigan , Michael Konevecki , Yung-Tin Chen , Raghuveer Makala , Vance Dunton
发明人： Natalie Nguyen , Paul Wai Kie Poon , Steven J. Radigan , Michael Konevecki , Yung-Tin Chen , Raghuveer Makala , Vance Dunton
IPC分类号： H01L21/82
CPC分类号： H01L21/0274 , H01L21/0337 , H01L27/1021 , Y10S438/947 , Y10S438/948 , Y10S438/949
摘要： A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.

96. 发明授权

US08222091B2 Damascene method of making a nonvolatile memory device 有权
标题翻译：制作非易失性存储器件的镶嵌方法
公开(公告)号：US08222091B2
公开(公告)日：2012-07-17
申请号：US13309857
申请日：2011-12-02
申请人： Vinod Robert Purayath , George Matamis , James Kai , Takashi Orimoto
发明人： Vinod Robert Purayath , George Matamis , James Kai , Takashi Orimoto
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L27/1021
摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.
摘要翻译：一种制造器件的方法包括提供包含由第一绝缘特征分开的第一半导体轨道的第一器件电平，在第一器件电平上形成牺牲层，在第一器件电平图形化牺牲层和第一半导体轨道以形成多个的第二轨道，其沿着第二方向延伸，其中所述多个第二轨道至少部分地延伸到所述第一装置水平面并且通过至少部分地延伸到所述第一装置水平的轨道形开口彼此分开，所述多个第二轨道，去除所述牺牲层，以及在所述第二设备水平上的第二设备水平的所述第二绝缘特征之间形成第二半导体轨道。第一半导体轨道沿第一方向延伸。第二半导体轨道沿与第一方向不同的第二方向延伸。

97. 发明授权

US08178286B2 Double patterning method 有权
标题翻译：双重图案化方法
公开(公告)号：US08178286B2
公开(公告)日：2012-05-15
申请号：US13155754
申请日：2011-06-08
申请人： Michael Chan
发明人： Michael Chan
IPC分类号： G03F7/26
CPC分类号： H01L21/0273 , H01L21/0331 , H01L21/3081 , H01L21/3086 , H01L21/31144 , H01L21/32139 , H01L27/101
摘要： A method of making a device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer to form a first photoresist pattern comprising a first grid, rendering the first photoresist pattern insoluble to a solvent, forming a second photoresist layer over the first photoresist pattern, patterning the second photoresist layer to form a second photoresist pattern over the underlying layer, where the second photoresist pattern is a second grid which overlaps the first grid to form a photoresist web, and etching the underlying layer using the photoresist web as a mask.
摘要翻译：制造器件的方法包括在下层上形成第一光致抗蚀剂层，图案化第一光致抗蚀剂层以形成包括第一栅格的第一光致抗蚀剂图案，使第一光致抗蚀剂图案不溶于溶剂，在第第一光致抗蚀剂图案，图案化第二光致抗蚀剂层以在下层上形成第二光致抗蚀剂图案，其中第二光致抗蚀剂图案是与第一栅格重叠以形成光致抗蚀剂幅材的第二栅格，并且使用光致抗蚀剂幅材蚀刻下层一个面具

98. 发明授权

US08154904B2 Programming reversible resistance switching elements 有权
标题翻译：编程可逆电阻开关元件
公开(公告)号：US08154904B2
公开(公告)日：2012-04-10
申请号：US12488159
申请日：2009-06-19
申请人： Deepak C. Sekar , Klaus Schuegraf , Roy Scheuerlein
发明人： Deepak C. Sekar , Klaus Schuegraf , Roy Scheuerlein
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C13/0007 , G11C7/00 , G11C8/12 , G11C13/0064 , G11C13/0069 , G11C2013/0076 , G11C2013/0088 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/72
摘要： A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption. In one embodiment, a page mapping scheme is provided that programs multiple memory cells in parallel in a way that reduces the worst case current and/or power consumption.
摘要翻译：描述了一种用于操作使用可逆电阻切换元件的存储系统的存储系统和方法。本文公开了用于改变编程条件以解决存储器单元具有的不同电阻的技术。这些技术可以以较少的尝试编程存储器单元，这可以节省时间和/或功率。本文公开了用于实现高编程带宽同时减少最坏情况下的电流和/或功率消耗的技术。在一个实施例中，提供了以减少最坏情况下的电流和/或功率消耗的方式并行地编程多个存储器单元的页面映射方案。

99. 发明申请

US20120077318A1 DAMASCENE METHOD OF MAKING A NONVOLATILE MEMORY DEVICE 有权
标题翻译：制造非易失性存储器件的DAMASCENE方法
公开(公告)号：US20120077318A1
公开(公告)日：2012-03-29
申请号：US13309857
申请日：2011-12-02
申请人： Vinod Robert PURAYATH , George MATAMIS , James KAI , Takashi ORIMOTO
发明人： Vinod Robert PURAYATH , George MATAMIS , James KAI , Takashi ORIMOTO
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L27/1021
摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.
摘要翻译：一种制造器件的方法包括提供包含由第一绝缘特征分开的第一半导体轨道的第一器件电平，在第一器件电平上形成牺牲层，在第一器件电平图形化牺牲层和第一半导体轨道以形成多个的第二轨道，其沿着第二方向延伸，其中所述多个第二轨道至少部分地延伸到所述第一装置水平面并且通过至少部分地延伸到所述第一装置水平的轨道形开口彼此分开，所述多个第二轨道，去除所述牺牲层，以及在所述第二设备水平上的第二设备水平的所述第二绝缘特征之间形成第二半导体轨道。第一半导体轨道沿第一方向延伸。第二半导体轨道沿与第一方向不同的第二方向延伸。

100. 发明授权

US08102694B2 Nonvolatile memory device containing carbon or nitrogen doped diode 失效
标题翻译：包含碳或氮掺杂二极管的非易失性存储器件
公开(公告)号：US08102694B2
公开(公告)日：2012-01-24
申请号：US11819042
申请日：2007-06-25
申请人： S. Brad Herner , Mark H. Clark , Tanmay Kumar
发明人： S. Brad Herner , Mark H. Clark , Tanmay Kumar
IPC分类号： G11C11/00 , G11C11/36
CPC分类号： G11C11/36
摘要： A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration.
摘要翻译：非易失性存储器件包括至少一个非易失性存储单元，其包括硅，锗或硅 - 锗二极管，其掺杂有浓度大于不可避免的杂质水平浓度的碳或氮中的至少一种。

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