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91. 发明申请

US20050233532A1 Method of forming sidewall spacers 审中-公开
标题翻译：形成侧墙的方法
公开(公告)号：US20050233532A1
公开(公告)日：2005-10-20
申请号：US11039084
申请日：2005-01-19
申请人： Markus Lenski , Falk Graetsch , Carsten Reichel , Christoph Schwan , Helmut Bierstedt , Thorsten Kammler , Martin Mazur
发明人： Markus Lenski , Falk Graetsch , Carsten Reichel , Christoph Schwan , Helmut Bierstedt , Thorsten Kammler , Martin Mazur
IPC分类号： H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/337 , H01L29/45 , H01L29/74 , H01L29/78 , H01L31/111
CPC分类号： H01L21/31144 , H01L21/32139 , H01L29/6659 , H01L29/7833
摘要： The present invention allows the formation of sidewall spacers adjacent a feature on a substrate without there being an undesirable erosion of the feature. The feature is covered by one or more protective layers. A layer of a spacer material is deposited over the feature and etched anisotropically. An etchant used in the anisotropic etching is adapted to selectively remove the spacer material, whereas the one or more protective layers are substantially not affected by the etchant. Thus, the one or more protective layers protect the feature from being exposed to the etchant.
摘要翻译：本发明允许在衬底上形成与特征相邻的侧壁间隔件，而不会有不希望的特征侵蚀。该特征被一个或多个保护层覆盖。隔离材料层沉积在特征上并各向异性地蚀刻。在各向异性蚀刻中使用的蚀刻剂适于选择性地去除间隔物材料，而一个或多个保护层基本上不受蚀刻剂的影响。因此，一个或多个保护层保护特征不暴露于蚀刻剂。

92. 发明申请

US20050212061A1 Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes 有权
标题翻译：通过使用分裂面形成绝缘体上半导体器件结构的方法
公开(公告)号：US20050212061A1
公开(公告)日：2005-09-29
申请号：US11127508
申请日：2005-05-12
申请人： Thomas Langdo , Matthew Currie , Richard Hammond , Anthony Lochtefeld , Eugene Fitzgerald
发明人： Thomas Langdo , Matthew Currie , Richard Hammond , Anthony Lochtefeld , Eugene Fitzgerald
IPC分类号： H01L21/20 , H01L21/331 , H01L21/336 , H01L21/337 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L29/76
CPC分类号： H01L29/7847 , H01L21/28518 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1033 , H01L29/165 , H01L29/41783 , H01L29/66242 , H01L29/66628 , H01L29/66772 , H01L29/66787 , H01L29/66916 , H01L29/7842 , H01L29/7843 , H01L29/7849 , H01L29/785 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译：应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

93. 发明申请

US20050189559A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050189559A1
公开(公告)日：2005-09-01
申请号：US10831130
申请日：2004-04-26
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L29/808 , H01L21/337 , H01L21/338 , H01L29/20 , H01L29/778 , H01L29/78 , H01L29/812 , H01L31/109
CPC分类号： H01L29/432 , H01L29/1066 , H01L29/2003 , H01L29/402 , H01L29/4236 , H01L29/7786 , H01L29/7787
摘要： A semiconductor device includes: a first semiconductor layer represented by a composition formula AlxGa1-xN(0≦x≦1); a first conductivity type or non-doped second semiconductor layer represented by a composition formula AlyGa1-yN (0≦y≦1, x
摘要翻译：半导体器件包括：由组成式Al x Ga 1-x N（0 <= x <= 1）表示的第一半导体层; 由组成式Al Y 1-y N（0 <= y <= 1，x

94. 发明申请

US20050158955A1 METHOD AND APPARATUS TO INCREASE STRAIN EFFECT IN A TRANSISTOR CHANNEL 有权
标题翻译：在晶体管通道中增加应变效应的方法和装置
公开(公告)号：US20050158955A1
公开(公告)日：2005-07-21
申请号：US10707842
申请日：2004-01-16
申请人： Haining Yang , Huilong Zhu
发明人： Haining Yang , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/337 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6653 , H01L29/66545 , H01L29/7842
摘要： A semiconductor device having a transistor channel with an enhanced stress is provided. To achieve the enhanced stress transistor channel, a nitride film is preferentially formed on the device substrate with little to no nitride on a portion of the gate stack. The nitride film may be preferentially deposited only on the silicon substrate in a non-conformal layer, where little to no nitride is deposited on the upper portions of the gate stack. The nitride film may also be uniformly deposited on the silicon substrate and gate stack in a conformal layer, with the nitride film proximate the upper regions of the gate stack preferentially removed in a later step. In some embodiments, nitride near the top of the gate stack is removed by removing the upper portion of the gate stack. In any of the methods, stress in the transistor channel is enhanced by minimizing nitride deposited on the gate stack, while having nitride deposited on the substrate.
摘要翻译：提供了具有增强应力的晶体管沟道的半导体器件。为了实现增强的应力晶体管沟道，在栅极堆叠的一部分上，在器件衬底上优先形成氮化物膜，几乎没有氮化物。氮化物膜可以优选仅在非保形层中沉积在硅衬底上，其中在栅堆叠的上部上沉积很少至无氮化物。氮化物膜也可以均匀地沉积在保形层上的硅衬底和栅极堆叠上，其中靠近栅极堆叠的上部区域的氮化物膜在稍后的步骤中优先被去除。在一些实施例中，通过去除栅极堆叠的上部来去除靠近栅极堆叠顶部的氮化物。在任何方法中，通过使沉积在栅极堆叠上的氮化物最小化，同时在衬底上沉积氮化物来增强晶体管沟道中的应力。

95. 发明申请

US20050158931A1 Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions 失效
标题翻译：制造应变半导体晶体管的方法，其具有位于源极和漏极区域之下的晶格失配的半导体区域
公开(公告)号：US20050158931A1
公开(公告)日：2005-07-21
申请号：US11081271
申请日：2005-03-16
申请人： Huajie Chen , Dureseti Chidambarrao , Oleg Gluschenkov , An Steegen , Haining Yang
发明人： Huajie Chen , Dureseti Chidambarrao , Oleg Gluschenkov , An Steegen , Haining Yang
IPC分类号： H01L21/20 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L21/337
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L27/1203 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
摘要翻译：提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。提供制造PFET和NFET的工艺。在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。

96. 发明申请

US20050156210A1 Methods of forming reacted conductive gate electrodes 有权
标题翻译：形成反应的导电栅电极的方法
公开(公告)号：US20050156210A1
公开(公告)日：2005-07-21
申请号：US11073976
申请日：2005-03-07
申请人： Matthew Currie , Richard Hammond
发明人： Matthew Currie , Richard Hammond
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L29/10 , H01L21/337 , H01L21/8234 , H01L29/94 , H01L31/113 , H01L21/3205
CPC分类号： H01L29/7848 , H01L21/28052 , H01L21/2807 , H01L21/28255 , H01L21/28518 , H01L21/324 , H01L29/0847 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/49 , H01L29/665 , H01L29/6659 , H01L29/7842
摘要： A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
摘要翻译：半导体器件和制造半导体器件的方法包括包括第一材料和第二材料的半导体层。第一和第二种材料可以是硅和锗。器件的触点具有靠近半导体层的部分和远离半导体层的部分。远侧部分包括第一材料和第二材料。与松弛的半导体层相邻并且邻近接触的远端部分形成的金属层与松弛的半导体层和接触的远端部分同时反应以提供金属接触材料。

97. 发明申请

US20050139871A1 Micro-electromechanical systems 失效
标题翻译：微机电系统
公开(公告)号：US20050139871A1
公开(公告)日：2005-06-30
申请号：US10508129
申请日：2003-03-19
申请人： Kevin Brunson , David Hamilton , Robert Tremayne Bunyan , Mark McNie
发明人： Kevin Brunson , David Hamilton , Robert Tremayne Bunyan , Mark McNie
IPC分类号： B81C1/00 , B81B7/02 , H01L21/337 , H01L27/095 , H01L29/808 , H01L29/80
CPC分类号： B81C1/00246 , B81C2203/0735
摘要： A MEMS incorporating a sensing element and a JFET electrically connected to the sensing element is fabricated by the steps of: forming a first layer of electrically insulating barrier material on a surface of a substrate; patterning the first layer so as to expose a first region of the substrate; doping by ion implantation the first region of the substrate to form a well region of the JFET; forming a second layer of barrier material on the surface of both the first layer and the first region of the substrate; patterning the barrier material so as to expose a part of the first region of the substrate; doping by ion implantation the exposed part of the first region of the substrate to form source and drain contact areas of the JFET; patterning the barrier material so as to expose a second region of the substrate; and doping by ion implantation the second region of the substrate to form gate and substrate contact areas of the JFET in a single implantion step. The monolithic integration of the JFET with the MEMS enables the bond wires for interconnecting the sensing element and the associated sensing electronic circuitry to be provided only after the buffering stage of such circuitry. This means that the bond wires interconnecting the buffering stage and the remainder of the circuitry are connected to a low impedance node which is less sensitive to noise and parasitic capacitive loading. Thus greater detection accuracy can be achieved by virtue of the fact that the parasitic capacitances are reduced to a minimum.
摘要翻译：通过以下步骤制造结合感测元件和电连接到感测元件的JFET的MEMS：在衬底的表面上形成第一层电绝缘阻挡材料; 图案化第一层以暴露衬底的第一区域; 通过离子注入掺杂衬底的第一区域以形成JFET的阱区; 在所述基板的所述第一层和所述第一区域的表面上形成第二层阻挡材料; 图案化所述阻挡材料以暴露所述基板的所述第一区域的一部分; 通过离子注入掺杂衬底的第一区域的暴露部分以形成JFET的源极和漏极接触区域; 图案化阻挡材料以暴露衬底的第二区域; 以及通过离子注入掺杂衬底的第二区域，以在单个注入步骤中形成JFET的栅极和衬底接触区域。 JFET与MEMS的单片集成使得仅在这种电路的缓冲级之后才提供用于将感测元件和相关联的感测电子电路互连的接合线。这意味着将缓冲级和电路的其余部分互连的接合线连接到对噪声和寄生电容负载较不敏感的低阻抗节点。因此，通过将寄生电容减小到最小的事实可以实现更高的检测精度。

98. 发明授权

US06905934B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06905934B2
公开(公告)日：2005-06-14
申请号：US10086689
申请日：2002-03-04
申请人： Takashi Hashimoto , Kouji Mikami , Tsutomu Udo , Masao Kondo , Eiji Oue
发明人： Takashi Hashimoto , Kouji Mikami , Tsutomu Udo , Masao Kondo , Eiji Oue
IPC分类号： H01L21/28 , H01L21/331 , H01L21/337 , H01L21/768 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L29/737 , H01L29/80
CPC分类号： H01L29/66916 , H01L21/8249 , H01L29/802
摘要： The invention provides a bipolar transistor with improved performance. An insulation film comprising a silicon oxide film is formed by means of oxidation treatment on the side surface of an emitter aperture, and then an epitaxial layer comprised of SiGe is grown selectively in an aperture formed by removing a silicon nitride film so as to form under cut.
摘要翻译：本发明提供了具有改进性能的双极晶体管。通过在发射器孔径的侧表面上进行氧化处理形成包含氧化硅膜的绝缘膜，然后选择性地在由除去氮化硅膜形成的孔中生长由SiGe组成的外延层，以形成下面切。

99. 发明授权

US06872609B1 Narrow bitline using Safier for mirrorbit 有权
标题翻译：使用Safier进行镜像位的窄位线
公开(公告)号：US06872609B1
公开(公告)日：2005-03-29
申请号：US10755430
申请日：2004-01-12
申请人： Tazrien Kamal , Weidong Qian , Kouros Ghandehari , Taraneh Jamali-Beh
发明人： Tazrien Kamal , Weidong Qian , Kouros Ghandehari , Taraneh Jamali-Beh
IPC分类号： H01L21/337 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/115
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. A Safier material is utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.
摘要翻译：公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。在形成过程中采用Safier材料以减小存储器中的埋置位线的尺寸，其适用于存储用于计算机等的数据。较小（例如较窄）的位线有助于增加打包密度，同时保持位线之间的有效通道长度。位线之间的间隔允许存储在电荷俘获层内的通道上方的双位保持充分分离，以便彼此不干扰。以这种方式，一个位可以被操作（例如，用于读取，写入或擦除操作）而基本上或不利地影响另一个位。此外，保留位分离，并且减轻了可能由窄通道产生的漏电流，串扰以及其他不利影响，并且允许存储器件根据需要进行操作。

100. 发明授权

US06858481B2 Memory device with active and passive layers 失效
标题翻译：具有主动和被动层的存储器件
公开(公告)号：US06858481B2
公开(公告)日：2005-02-22
申请号：US10413818
申请日：2003-04-15
申请人： Juri H. Krieger , Nikolai Yudanov
发明人： Juri H. Krieger , Nikolai Yudanov
IPC分类号： G11C11/34 , G11C11/56 , G11C13/02 , H01L27/28 , H01L51/00 , H01L51/30 , H01L21/337
CPC分类号： G11C11/34 , B82Y10/00 , G11C11/5664 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C13/0064 , G11C13/0069 , G11C13/04 , G11C2213/11 , G11C2213/12 , G11C2213/15 , G11C2213/34 , G11C2213/35 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/77 , H01L27/28 , H01L27/285 , H01L45/04 , H01L45/145 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0041 , H01L51/0042 , H01L51/0051 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0094 , H01L51/0595
摘要： A memory including memory cells having active and passive layers may store multiple information bits. The active layer may include an organic polymer that has a variable resistance based on the movement of charged species (ions or ions and electrons) between the passive layer and the active layer. The passive layer may be a super-ionic material that has high ion and electron mobility. The active layer may be self-assembled from a monomer in a liquid or gas.
摘要翻译：包括具有有源层和无源层的存储单元的存储器可以存储多个信息位。有源层可以包括有机聚合物，其基于被动层与有源层之间的带电物质（离子或离子和电子）的移动而具有可变电阻。钝化层可以是具有高离子和电子迁移率的超离子材料。活性层可以从液体或气体中的单体自组装。

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