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    • 93. 发明申请
      US20050018786A1 Interleaved trellis coded modulation and decoding 审中-公开
    • Interleaved trellis coded modulation and decoding
    • 交织网格编码调制解码
    • US20050018786A1
    • 2005-01-27
    • US10897893
    • 2004-07-21
    • Keshab Parhi , Yongru Gu
    • Keshab Parhi , Yongru Gu
    • H04L1/00 , H04L25/14 , H04L5/12
    • H04L1/0071 , H04L1/0045 , H04L1/006 , H04L25/14
    • Digital communications systems employ trellis coded modulation schemes. A K-dimensional trellis coded modulated symbol is transmitted over M channels in K/M cycles (where M divides K). K/M consecutive data units are transmitted serially in a time multiplexed manner in K/M consecutive cycles over one channel. If M=1, then each symbol is transmitted over one channel in K cycles in a time-multiplexed manner. At the receiver, a symbol is formed by grouping the data received from M channels in K/M cycles and this symbol is then decoded by a joint equalizer and decoder. If the number of parallel channels is N, then N/M trellis coded modulators and N/M decoders can be used in parallel. The advantage of this approach is an increase in speed by factor N/M. The N/M trellis coded modulation and joint equalization and decoding operations can also be implemented by using fewer hardware trellis coded modulators and decoders using folding technique where multiple operations are time-multiplexed to the same hardware modulator or decoder which are operated by higher clock speed.
    • 数字通信系统采用网格编码调制方案。 K维网格编码调制符号以K / M周期的M个信道发送（其中M除以K）。 通过一个通道以K / M个连续周期的时间复用方式串行发送K / M个连续的数据单元。 如果M = 1，则以K个周期的时间复用方式在一个信道上发送每个符号。 在接收机处，通过以K / M个周期对从M个信道接收到的数据进行分组而形成符号，然后由联合均衡器和解码器对该符号进行解码。 如果并行通道数为N，则N / M网格编码调制器和N / M解码器可以并行使用。 这种方法的优点是以因子N / M提高速度。 N / M网格编码调制和联合均衡和解码操作也可以通过使用较少的硬件网格编码调制器和解码器来实现，该技术使用折叠技术，其中多个操作被时分复用到由较高时钟速度操作的相同硬件调制器或解码器 。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 95. 发明授权
      US06160819A Method and apparatus for multiplexing bytes over parallel communications links using data slices 失效
    • Method and apparatus for multiplexing bytes over parallel communications links using data slices
    • 用于通过并行通信链路使用数据片复用字节的方法和装置
    • US06160819A
    • 2000-12-12
    • US26269
    • 1998-02-19
    • Craig Partridge , Walter C. Milliken
    • Craig Partridge , Walter C. Milliken
    • H04J14/02 , H04L25/14 , H04J3/00
    • H04L25/14 , H04J14/02 , H04Q2213/13093 , H04Q2213/13106 , H04Q2213/13174 , H04Q2213/13204 , H04Q2213/13216 , H04Q2213/1329 , H04Q2213/13292 , H04Q2213/13295 , H04Q2213/13322 , H04Q2213/13367 , H04Q2213/13386 , H04Q2213/13389
    • A communication technique for transmitting packet data over parallel communication sublinks coupled to a processor unit is provided. Initially, a method receives a packet of data from a first communication link which is coupled to a set of sublinks. The method distributes packets over each of the sublinks utilizing a unique byte-by-byte (BBB) striping technique. Logically, the data bytes associated with each sublink are collected into a slice of data and each set of slices are given a unique predetermined label. Each slice is then synchronously transmitted at the aggregate bandwidth of each sublink in parallel across each corresponding sublink to a receiver. A receiver receives the slices of data from the set of sublinks and aggregates the bandwidth of these two or more communication sublinks into a single communication link. Unless there are errors, a packet is transmitted in order using multiple slices. The system recreates the original packet of data from sets of slices having the same unique label. Specifically, the system uses the byte-by-byte striping technique to extract the appropriate bytes of information from each slice received over the parallel sublinks based upon a predetermined sublink sequence corresponding to the labels. This technique is advantageous in that it provides an optimal balance between preserving packet order and conserving network resources.
    • 提供了一种用于通过耦合到处理器单元的并行通信子链路来发送分组数据的通信技术。 最初，方法从第一通信链路接收数据分组，第一通信链路耦合到一组子链路。 该方法使用唯一的逐字节（BBB）条带化技术来分配每个子链路上的分组。 在逻辑上，与每个子链接相关联的数据字节被收集到数据片中，并且每组片段被赋予唯一的预定标签。 然后每个片段以每个子链路的聚合带宽并行地跨每个对应的子链路同步发送到接收机。 接收器从该子集合接收数据片段，并将这两个或更多个通信子链路的带宽聚合成单个通信链路。 除非有错误，否则使用多个片段按顺序传输数据包。 系统从具有相同唯一标签的片组重新创建原始数据包。 具体地，系统使用逐字节条带化技术，基于与标签相对应的预定子链接序列，从并行子链接中接收的每个切片提取信息的适当字节。 这种技术的优点在于它在保持分组顺序和节省网络资源之间提供了最佳平衡。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 97. 发明授权
      US6011808A Redundant codes for clock recovery in serial links 失效
    • Redundant codes for clock recovery in serial links
    • 冗余代码用于串行链路中的时钟恢复
    • US6011808A
    • 2000-01-04
    • US787835
    • 1997-01-23
    • Patrik Larsson , Per Magnusson
    • Patrik Larsson , Per Magnusson
    • H04L25/14 , H04J3/06
    • H04L25/14
    • The amount of jitter that results in a serial receiver having a parallel architecture Can is reduced by insuring that the edges specifically introduced by the code are actually received by the phase detector. In particular, the code is designed to increase the probability that the edges it introduces are actually received by the phase detector. In a preferred embodiment of the invention, all the edges introduced by the code are actually received by the phase detector. This is achieved by guaranteeing that the edges introduced by the code are evenly spaced in the data stream at a rate corresponding to the phase detector sampling rate. For example, if the receiver consists of N data samplers, e.g., N=5, and one phase detector, the edges introduced by the code are arranged to be N symbols apart. This may be done by inserting as the Nth symbol an overall symbol that has a dummy component so that an edge results between the N-1 symbol and the overall Nth symbol. Thus, the data stream is arranged into repeating frames of N symbols. Alternatively, the frame could be arranged to be a multiple X of N, e.g., the frame is K symbols long, K=XN, with the partially redundant data symbol being the K-1, i.e., XN-1, symbol.
    • 导致具有并行架构Can的串行接收机的抖动量通过确保由代码特别引入的边缘实际上被相位检测器接收来减少。 特别地，代码被设计为增加其引入的边缘实际上被相位检测器接收的概率。 在本发明的优选实施例中，由代码引入的所有边缘实际上由相位检测器接收。 这是通过保证由代码引入的边缘以对应于相位检测器采样率的速率在数据流中均匀地间隔来实现的。 例如，如果接收机由N个数据采样器（例如N = 5）和一个相位检测器组成，则由码引入的边被排列成N个符号。 这可以通过将第N个符号插入具有虚拟分量的全部符号，使得在N-1个符号和第N个符号之间产生边缘来完成。 因此，数据流被排列成N个符号的重复帧。 或者，该帧可以被布置为N的倍数X，例如，该帧是K个符号长，K = XN，部分冗余数据符号是K-1，即XN-1符号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 98. 发明授权
      US5978419A Transmitter and receiver circuits for high-speed parallel digital data transmission link 失效
    • Transmitter and receiver circuits for high-speed parallel digital data transmission link
    • US5978419A
    • 1999-11-02
    • US881471
    • 1997-06-24
    • Daniel R. Cassiday , Soroush Shakib , Derek Tsai , Mistsuo Magane , Katsushi Asahina
    • Daniel R. Cassiday , Soroush Shakib , Derek Tsai , Mistsuo Magane , Katsushi Asahina
    • H04L25/02 , G06F1/12 , H04L1/24 , H04L25/14 , H04L25/40 , H04B3/00
    • H04L25/14 , G06F1/12 , H04L1/24
    • An information transfer system includes a transmitter and a receiver for transferring information over a differential communication link. The transmitter circuit includes a plurality of gated driver circuits each associated with one of a plurality separate phases of a clock signal, all of the gated driver circuits having respective outputs connected to a differential driver. Each gated driver circuit receives at a respective input a respective one of a plurality of selected information signals and transmits it over the communication link in response to the associated clock signal phase. A plurality of information selectors, each associated one of the gated driver circuits, are connected to receive a plurality of information signals each from a respective one of a plurality of digital information sources and selectively couple one of the information signals to the associated gated driver circuit as the respective selected information signal during a clock signal phase ahead of the clock signal phase ahead of the clock signal phase with which the associated gated driver circuit is associated. The receiver circuit includes a differential receiver which generates a single-ended signal representative of digital data in response the differential signals transmitted over the wires comprising the differential communication link. The differential receiver has a plurality of inputs each for connection to one of the wires of the differential communication link. A termination resistor is connected between the differential receiver inputs, and a continuity test circuit applies a test voltage to one of the differential receiver inputs during a link test operation. The digital receiver generates the single ended signal representative of digital data provided by the transmitter circuit the appropriate digital data value if the wires are continuous between the transmitter circuit and the receiver circuit. However, if at least one of the wires is not continuous, the differential receiver will provide a single-ended signal representative of the wrong digital data value.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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