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11. 发明授权

US07689887B2 Automatic shutdown or throttling of a BIST state machine using thermal feedback 失效
标题翻译：使用热反馈自动关闭或调节BIST状态机
公开(公告)号：US07689887B2
公开(公告)日：2010-03-30
申请号：US11962781
申请日：2007-12-21
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
IPC分类号： G06F11/00 , G06F13/24 , G01R31/28 , G01R31/00 , G01R31/02
CPC分类号： G11C29/14 , G01K3/005 , G11C29/12 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodied in a machine readable medium are provided. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译：内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关联的BIST测试操作，以及包括BIST的设计结构提供了体现在机器可读介质中的状态机。热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。

12. 发明申请

US20090161722A1 AUTOMATIC SHUTDOWN OR THROTTLING OF A BIST STATE MACHINE USING THERMAL FEEDBACK 失效
标题翻译：使用热反馈自动关机或弯曲状态机
公开(公告)号：US20090161722A1
公开(公告)日：2009-06-25
申请号：US11962781
申请日：2007-12-21
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
IPC分类号： G01K13/00
CPC分类号： G11C29/14 , G01K3/005 , G11C29/12 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodied in a machine readable medium are provided. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译：内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关联的BIST测试操作，以及包括BIST的设计结构提供了体现在机器可读介质中的状态机。热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。

13. 发明申请

US20090052609A1 METHOD AND APPARATUS FOR SELF IDENTIFICATION OF CIRCUITRY 有权
标题翻译：自动识别电路的方法和装置
公开(公告)号：US20090052609A1
公开(公告)日：2009-02-26
申请号：US11841125
申请日：2007-08-20
申请人： Valerie Hornbeck Chickanosky , Kevin William Gorman , Emory D. Keller , Michael Richard Ouellette
发明人： Valerie Hornbeck Chickanosky , Kevin William Gorman , Emory D. Keller , Michael Richard Ouellette
IPC分类号： G01F15/06
CPC分类号： G01R31/31724 , G01R31/31721
摘要： A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.
摘要翻译：一种包括用于启用枚举操作的控制器的系统。枚举操作由系统中的控制器（110）和逻辑元件（120）执行，使得系统中的每个逻辑元件分配自身唯一的标识符。然后，每个逻辑元件可以被另一个源控制，或者具有与系统中的其它逻辑元件通信的手段。独特的标识符可以实现更大的系统灵活性，从而降低成本并提高效率。

14. 发明申请

US20080222464A1 Structure for System for and Method of Performing High Speed Memory Diagnostics Via Built-In-Self-Test 失效
标题翻译：通过内置自检执行高速内存诊断的系统和方法的结构
公开(公告)号：US20080222464A1
公开(公告)日：2008-09-11
申请号：US12126452
申请日：2008-05-23
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/40 , G01R31/31703 , G01R31/31704 , G11C2029/3202
摘要： A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译：公开了一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法的设计结构。特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。

15. 发明授权

US06978234B1 Configurable real prototype hardware using cores and memory macros 失效
标题翻译：可配置的真实原型硬件使用内核和内存宏
公开(公告)号：US06978234B1
公开(公告)日：2005-12-20
申请号：US09602369
申请日：2000-06-23
申请人： Robert P. Battaline , Emory D. Keller , Sebastian T. Ventrone
发明人： Robert P. Battaline , Emory D. Keller , Sebastian T. Ventrone
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22 , G06F11/26 , G06F13/00
CPC分类号： G06F11/261
摘要： A method of creating a prototype data processing system, by configuring a hardware development chip (HDC) according to user-defined settings, building user-defined logic adapted to function with the configured development chip, and allowing for the re-configuration of the HDC and user-defined logic after debugging. The HDC has several data processing macros including a processor core macro, a ROM emulation macro, a memory macro, and a bus macro. The macros may be configured by a configuration pin block which is connected to external configuration pins on the HDC. Customer logic is built using a field programmable gate array, which is interconnected with external ports of the HDC. The HDC and customer logic are verified using a debug port on the HDC, which is connected to a debug workstation. The invention allows a user to easily and quickly debug an application-specific integrated circuit (ASIC) design with a unique version of selected processor cores.
摘要翻译：一种创建原型数据处理系统的方法，通过根据用户定义的设置配置硬件开发芯片（HDC），构建适用于配置的开发芯片的用户定义逻辑，并允许重新配置HDC 和调试后的用户定义逻辑。 HDC具有多个数据处理宏，包括处理器核心宏，ROM仿真宏，存储器宏和总线宏。宏可以由连接到HDC上的外部配置引脚的配置引脚块来配置。客户逻辑使用与HDC的外部端口互连的现场可编程门阵列构建。 HDC和客户逻辑使用HDC上的调试端口进行验证，该调试端口连接到调试工作站。本发明允许用户使用所选择的处理器核心的唯一版本容易且快速地调试专用集成电路（ASIC）设计。

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