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1. 发明申请

US20080082883A1 SYSTEM FOR AND METHOD OF PERFORMING HIGH SPEED MEMORY DIAGNOSTICS VIA BUILT-IN-SELF-TEST 有权
标题翻译：通过内置自检来执行高速记忆诊断的系统和方法
公开(公告)号：US20080082883A1
公开(公告)日：2008-04-03
申请号：US11531035
申请日：2006-09-12
申请人： Kevin W Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
发明人： Kevin W Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G01R31/28
CPC分类号： G11C29/44 , G11C2029/3202
摘要： A system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译：公开了一种通过内置自检（BIST）执行高速存储器诊断的系统和方法。特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。

2. 发明授权

US07870454B2 Structure for system for and method of performing high speed memory diagnostics via built-in-self-test 失效
标题翻译：用于通过内置自检进行高速存储器诊断的系统和方法的结构
公开(公告)号：US07870454B2
公开(公告)日：2011-01-11
申请号：US12126452
申请日：2008-05-23
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G01R31/28 , G11C21/00
CPC分类号： G11C29/40 , G01R31/31703 , G01R31/31704 , G11C2029/3202
摘要： A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译：公开了一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法的设计结构。特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。

3. 发明授权

US07607060B2 System and method for performing high speed memory diagnostics via built-in-self-test 有权
标题翻译：通过内置自检进行高速存储器诊断的系统和方法
公开(公告)号：US07607060B2
公开(公告)日：2009-10-20
申请号：US11531035
申请日：2006-09-12
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/44 , G11C2029/3202
摘要： A system and method for performing high speed memory diagnostics via built-in-self-test (BIST). A test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method includes presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm, performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译：一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法。测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。一种方法包括预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑等待时间的值，将BIST周期计数器设置为递减模式，将可变延迟预置为零，重新执行测试算法，执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。

4. 发明申请

US20080222464A1 Structure for System for and Method of Performing High Speed Memory Diagnostics Via Built-In-Self-Test 失效
标题翻译：通过内置自检执行高速内存诊断的系统和方法的结构
公开(公告)号：US20080222464A1
公开(公告)日：2008-09-11
申请号：US12126452
申请日：2008-05-23
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/40 , G01R31/31703 , G01R31/31704 , G11C2029/3202
摘要： A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译：公开了一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法的设计结构。特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。

5. 发明授权

US07458000B2 Automatic shutdown or throttling of a bist state machine using thermal feedback 失效
标题翻译：使用热反馈自动关闭或调节双速状态机
公开(公告)号：US07458000B2
公开(公告)日：2008-11-25
申请号：US11278238
申请日：2006-03-31
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译：内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关的BIST测试操作。热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。

6. 发明授权

US07689887B2 Automatic shutdown or throttling of a BIST state machine using thermal feedback 失效
标题翻译：使用热反馈自动关闭或调节BIST状态机
公开(公告)号：US07689887B2
公开(公告)日：2010-03-30
申请号：US11962781
申请日：2007-12-21
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
IPC分类号： G06F11/00 , G06F13/24 , G01R31/28 , G01R31/00 , G01R31/02
CPC分类号： G11C29/14 , G01K3/005 , G11C29/12 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodied in a machine readable medium are provided. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译：内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关联的BIST测试操作，以及包括BIST的设计结构提供了体现在机器可读介质中的状态机。热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。

7. 发明申请

US20090161722A1 AUTOMATIC SHUTDOWN OR THROTTLING OF A BIST STATE MACHINE USING THERMAL FEEDBACK 失效
标题翻译：使用热反馈自动关机或弯曲状态机
公开(公告)号：US20090161722A1
公开(公告)日：2009-06-25
申请号：US11962781
申请日：2007-12-21
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
IPC分类号： G01K13/00
CPC分类号： G11C29/14 , G01K3/005 , G11C29/12 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodied in a machine readable medium are provided. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译：内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关联的BIST测试操作，以及包括BIST的设计结构提供了体现在机器可读介质中的状态机。热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。

8. 发明授权

US07916826B2 Diagnostic method and apparatus for non-destructively observing latch data 有权
标题翻译：用于非破坏性观察锁存数据的诊断方法和装置
公开(公告)号：US07916826B2
公开(公告)日：2011-03-29
申请号：US12175534
申请日：2008-07-18
申请人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
发明人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译：本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。该电路包括连接到移位寄存器的输入和输出的选择器。选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。控制装置还包括从电路外部可访问的数据输出。观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

9. 发明授权

US06768694B2 Method of electrically blowing fuses under control of an on-chip tester interface apparatus 有权
标题翻译：在片上测试仪接口装置的控制下电熔熔丝的方法
公开(公告)号：US06768694B2
公开(公告)日：2004-07-27
申请号：US10265591
申请日：2002-10-07
申请人： Darren L. Anand , Bruce Cowan , L. Owen Farnsworth, III , Pamela S. Gillis , Peter O. Jakobsen , Krishnendu Mondal , Steven F. Oakland , Michael R. Ouellette , Donald L. Wheater
发明人： Darren L. Anand , Bruce Cowan , L. Owen Farnsworth, III , Pamela S. Gillis , Peter O. Jakobsen , Krishnendu Mondal , Steven F. Oakland , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G11C700
CPC分类号： G11C29/027 , G11C17/18 , G11C29/56 , G11C29/785 , G11C2029/1208
摘要： A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.
摘要翻译：公开了一种芯片修复系统，专为自动化测试设备而独立应用于许多独特的非常密集的ASIC设备，在高周转环境中。在测试期间，系统将控制芯片内置的自检（BIST）引擎收集和压缩修复数据，程序保险丝，并最终解压缩并重新加载后保险丝测试的修复数据。在最终使用应用程序中，该系统在上电时或在系统请求下解压缩加载修复数据。

10. 发明申请

US20090180584A1 DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LATCH DATA 有权
标题翻译：诊断方法和装置，用于非分析性观察数据
公开(公告)号：US20090180584A1
公开(公告)日：2009-07-16
申请号：US12175534
申请日：2008-07-18
申请人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
发明人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译：本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。该电路包括连接到移位寄存器的输入和输出的选择器。选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。控制装置还包括从电路外部可访问的数据输出。观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

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