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1. 发明授权

US07458000B2 Automatic shutdown or throttling of a bist state machine using thermal feedback 失效
标题翻译：使用热反馈自动关闭或调节双速状态机
公开(公告)号：US07458000B2
公开(公告)日：2008-11-25
申请号：US11278238
申请日：2006-03-31
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译：内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关的BIST测试操作。热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。

2. 发明申请

US20080082883A1 SYSTEM FOR AND METHOD OF PERFORMING HIGH SPEED MEMORY DIAGNOSTICS VIA BUILT-IN-SELF-TEST 有权
标题翻译：通过内置自检来执行高速记忆诊断的系统和方法
公开(公告)号：US20080082883A1
公开(公告)日：2008-04-03
申请号：US11531035
申请日：2006-09-12
申请人： Kevin W Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
发明人： Kevin W Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G01R31/28
CPC分类号： G11C29/44 , G11C2029/3202
摘要： A system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译：公开了一种通过内置自检（BIST）执行高速存储器诊断的系统和方法。特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。

3. 发明授权

US07870454B2 Structure for system for and method of performing high speed memory diagnostics via built-in-self-test 失效
标题翻译：用于通过内置自检进行高速存储器诊断的系统和方法的结构
公开(公告)号：US07870454B2
公开(公告)日：2011-01-11
申请号：US12126452
申请日：2008-05-23
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G01R31/28 , G11C21/00
CPC分类号： G11C29/40 , G01R31/31703 , G01R31/31704 , G11C2029/3202
摘要： A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译：公开了一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法的设计结构。特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。

4. 发明授权

US07607060B2 System and method for performing high speed memory diagnostics via built-in-self-test 有权
标题翻译：通过内置自检进行高速存储器诊断的系统和方法
公开(公告)号：US07607060B2
公开(公告)日：2009-10-20
申请号：US11531035
申请日：2006-09-12
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/44 , G11C2029/3202
摘要： A system and method for performing high speed memory diagnostics via built-in-self-test (BIST). A test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method includes presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm, performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译：一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法。测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。一种方法包括预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑等待时间的值，将BIST周期计数器设置为递减模式，将可变延迟预置为零，重新执行测试算法，执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。

5. 发明授权

US07689887B2 Automatic shutdown or throttling of a BIST state machine using thermal feedback 失效
标题翻译：使用热反馈自动关闭或调节BIST状态机
公开(公告)号：US07689887B2
公开(公告)日：2010-03-30
申请号：US11962781
申请日：2007-12-21
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
IPC分类号： G06F11/00 , G06F13/24 , G01R31/28 , G01R31/00 , G01R31/02
CPC分类号： G11C29/14 , G01K3/005 , G11C29/12 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodied in a machine readable medium are provided. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译：内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关联的BIST测试操作，以及包括BIST的设计结构提供了体现在机器可读介质中的状态机。热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。

6. 发明申请

US20090161722A1 AUTOMATIC SHUTDOWN OR THROTTLING OF A BIST STATE MACHINE USING THERMAL FEEDBACK 失效
标题翻译：使用热反馈自动关机或弯曲状态机
公开(公告)号：US20090161722A1
公开(公告)日：2009-06-25
申请号：US11962781
申请日：2007-12-21
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette
IPC分类号： G01K13/00
CPC分类号： G11C29/14 , G01K3/005 , G11C29/12 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodied in a machine readable medium are provided. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译：内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关联的BIST测试操作，以及包括BIST的设计结构提供了体现在机器可读介质中的状态机。热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。

7. 发明申请

US20080222464A1 Structure for System for and Method of Performing High Speed Memory Diagnostics Via Built-In-Self-Test 失效
标题翻译：通过内置自检执行高速内存诊断的系统和方法的结构
公开(公告)号：US20080222464A1
公开(公告)日：2008-09-11
申请号：US12126452
申请日：2008-05-23
申请人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
发明人： Kevin W. Gorman , Emory D. Keller , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/40 , G01R31/31703 , G01R31/31704 , G11C2029/3202
摘要： A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译：公开了一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法的设计结构。特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。

8. 发明授权

US08467260B2 Structure and method for storing multiple repair pass data into a fusebay 有权
标题翻译：用于将多个修复传递数据存储到保险丝盒中的结构和方法
公开(公告)号：US08467260B2
公开(公告)日：2013-06-18
申请号：US13198894
申请日：2011-08-05
申请人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C29/785 , G11C29/802
摘要： Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.
摘要翻译：相同页数的保险丝宏串联地形成相同数量的保险丝页，每个保险丝页的长度等于相应的熔丝宏页面长度之和。每个保险丝宏都有一个使能锁存器，配置为允许一次激活一个保险丝宏。连接到维修寄存器的保险丝控制装置可以将数据存储在保险丝盒中并从熔丝座检索数据。在编程模式下确定下一个可用的熔丝位置，以便下一个维修通过的数据可以在最后一个数据结束的地方开始。

9. 发明授权

US08917566B2 Bypass structure for a memory device and method to reduce unknown test values 有权
标题翻译：用于存储器件的旁路结构和减少未知测试值的方法
公开(公告)号：US08917566B2
公开(公告)日：2014-12-23
申请号：US13444229
申请日：2012-04-11
申请人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
发明人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
IPC分类号： G11C7/00
CPC分类号： G11C29/56004
摘要： Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.
摘要翻译：本发明的方面提供了一种用于减少未知测试值的存储器件的旁路结构以及相关方法。在一个实施例中，公开了一种用于存储器件的旁路结构。旁路结构包括：逻辑门，被配置为接收测试信号和时钟信号; 以及输出锁存器，被配置为接收逻辑门的输出，存储器件的输出和旁路数据信号，其中输出锁存器被配置为保持旁路数据信号并且绕过存储器件的输出以响应于断言测试信号，使得来自存储器设备的输出的未知数据被旁路。

10. 发明授权

US08719648B2 Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture 失效
标题翻译：在单个保险丝架构中交织内存修复数据压缩和保险丝编程操作
公开(公告)号：US08719648B2
公开(公告)日：2014-05-06
申请号：US13192051
申请日：2011-07-27
申请人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C29/00
CPC分类号： G11C29/785 , G11C2029/0409 , H03M7/30
摘要： An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data.
摘要翻译：描述了在单个熔丝架结构中交织存储器修复数据压缩和熔丝编程操作的方法。在一个实施例中，单个熔丝架结构包括与处理存储器修复数据压缩和熔丝编程操作的分割和交织方法一起使用的多页。特别地，对于单个熔丝架结构中的每个页面，对存储器修复数据执行存储器修复数据压缩操作，随后对压缩存储器修复数据执行熔丝编程操作。

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