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11. 发明授权

US09954538B2 Clock alignment scheme for data macros of DDR PHY 有权
公开(公告)号：US09954538B2
公开(公告)日：2018-04-24
申请号：US15192594
申请日：2016-06-24
申请人： Invecas, Inc.
发明人： Narasimhan Vasudevan , Venkata N. S. N. Rao , Prasad Chalasani
IPC分类号： H03L7/06 , H03L7/081 , H03L7/083 , H03L7/091 , G11C11/4063 , G11C7/22
CPC分类号： H03L7/0818 , G11C7/222 , G11C11/4063 , G11C11/4076 , H03L7/0812 , H03L7/083 , H03L7/085 , H03L7/089 , H03L7/091
摘要： A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.

12. 发明申请

US20170316837A1 Diagnostics for a Memory Device 有权
公开(公告)号：US20170316837A1
公开(公告)日：2017-11-02
申请号：US15140242
申请日：2016-04-27
申请人： Invecas, Inc.
发明人： Thomas Chadwick , Kevin W. Gorman , Nancy Pratt
IPC分类号： G11C29/38 , G11C29/44
CPC分类号： G11C29/38 , G11C29/44 , G11C2029/3202
摘要： A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test (“MUT”). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.

13. 发明授权

US09716492B1 Method and circuit for duty cycle detection 有权
公开(公告)号：US09716492B1
公开(公告)日：2017-07-25
申请号：US15241664
申请日：2016-08-19
申请人： Invecas, Inc.
发明人： Venkata N. S. N. Rao
IPC分类号： H03K5/22 , H03K5/156 , H03K5/26
CPC分类号： H03K5/1565 , H03K5/26
摘要： A duty cycle detection circuit, comprises a charge storage component and compare logic. The charge storage component has at least one capacitor, at least one switch, and, at least one current source. A clock signal is used to operate the at least one switch for charging the at least one capacitor using the at least one current source. The charge storage component outputs a first signal indicative of an amount of charge stored when the clock signal is logic high and a second signal indicative of an amount of charge stored when the clock signal is logic low. The compare logic compares the first signal and the second signal to determine a duty cycle for the clock signal.

14. 发明授权

US10498351B1 High-speed DAC 有权
公开(公告)号：US10498351B1
公开(公告)日：2019-12-03
申请号：US15989081
申请日：2018-05-24
申请人： Invecas, Inc.
发明人： Koushik De , Pramod Kumar Chennoju
IPC分类号： H03M1/76 , H03M1/74 , H03M1/10
CPC分类号： H03M1/765 , H03M1/1061 , H03M1/747
摘要： A digital-to-analog converter (“DAC”) system for converting a digital input code to an analog signal, comprises: an N-bit DAC and a back-gate bias generator (“BBGEN”). The N-bit DAC has a reference cell and a current source array of unit cells for generating a DAC output. The (“BBGEN”) generates a first back-gate bias voltage PB_CSM and a second back-gate bias voltage PB_CSA. A back gate of the reference cell is configured to receive the first back-gate bias voltage PB_CSM. A back gate of each of the unit cells is configured to receive the second back-gate bias voltage PB_CSA. The reference cell is configured to generate a main current, and the unit cells are configured to mirror the main current.

15. 发明申请

US20190268193A1 PWM Demodulation 审中-公开
公开(公告)号：US20190268193A1
公开(公告)日：2019-08-29
申请号：US15904139
申请日：2018-02-23
申请人： Invecas, Inc.
发明人： SIVA KUMAR RAPINA , SARAVANA KUMAR DURAIRAJ
IPC分类号： H04L27/156 , H03K9/08 , H03K5/003
摘要： A receiver for demodulating a pulse width modulated (“PWM”) signal, comprises: a voltage level shifter for shifting the PWM signal to predefined transistor voltage levels; a half-rate PWM decoder for receiving the shifted PWM signal; and a 2-bit-to-N-bit deserializer. The half-rate PWM decoder comprises a first decoder core, a second decoder core, a controller, and a sampler and retiming circuit. The first decoder core and the second decoder core are configured to decode alternating periods of the shifted PWM signal. The controller is coupled to the first decoder core, the second decoder core, the sampler and retiming circuit. The retiming circuit is configured to receive clock signals from the controller and to output half-rate even data from the first decoder core and half-rate odd data from the second decoder core. Outputs of the retiming circuit and an output of the controller are coupled to inputs of the deserializer.

16. 发明授权

US10014866B2 Clock alignment scheme for data macros of DDR PHY 有权
公开(公告)号：US10014866B2
公开(公告)日：2018-07-03
申请号：US15707205
申请日：2017-09-18
申请人： Invecas, Inc.
发明人： Narasimhan Vasudevan , Venkata N. S. N. Rao , Prasad Chalasani
IPC分类号： H03L7/06 , H03L7/081 , G11C11/4063 , H03L7/083 , G11C7/22 , H03L7/091
CPC分类号： H03L7/0818 , G11C7/222 , G11C11/4063 , G11C11/4076 , H03L7/0812 , H03L7/083 , H03L7/085 , H03L7/089 , H03L7/091
摘要： A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.

17. 发明授权

US09946620B2 Memory built-in self test system 有权
公开(公告)号：US09946620B2
公开(公告)日：2018-04-17
申请号：US15012707
申请日：2016-02-01
申请人： Invecas, Inc.
发明人： Kevin W. Gorman , Thomas Chadwick , Nancy Pratt
IPC分类号： G11C29/00 , G01R31/28 , G06F11/263 , G11C29/16 , G11C29/14 , G11C29/04
CPC分类号： G06F11/263 , G11C29/14 , G11C29/16 , G11C2029/0401
摘要： A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.

18. 发明申请

US20170323222A1 Optimal Data Eye for Improved Vref Margin 有权
公开(公告)号：US20170323222A1
公开(公告)日：2017-11-09
申请号：US15467775
申请日：2017-03-23
申请人： Invecas, Inc.
发明人： Venkata N.S.N. Rao , Ravindra Kantamani , Prasad Chalasani
IPC分类号： G06N99/00 , G11C7/22
CPC分类号： G06N99/005 , G11C5/063 , G11C7/00 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/10 , G11C29/36 , G11C2029/3602 , G11C2207/2254
摘要： An optimized method, system, and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.

19. 发明授权

US09564180B1 Deep-sleep wake up for a memory device 有权
标题翻译：深度睡眠唤醒记忆体设备
公开(公告)号：US09564180B1
公开(公告)日：2017-02-07
申请号：US15192697
申请日：2016-06-24
申请人： Invecas, Inc.
发明人： Harold Pilo , Michael Lee
IPC分类号： G11C5/14
CPC分类号： G11C5/148
摘要： A memory device comprises memory banks, power gates, and bank wake-up circuits. Each of the memory banks has a core voltage supply. The power gates are coupled to the memory banks for charging the core voltage supplies and have a plurality of powering modes. The bank wake-up circuits are coupled to the power gates for selecting one of the plurality of power modes for charging the memory banks during a wake-up mode. The bank wake-up circuits sense the core voltage supplies during the wake-up mode. The bank wake-up circuits serially charge the memory banks as a function of the sensed core voltage supplies of the memory banks.
摘要翻译：存储器件包括存储器组，电源门和存储体唤醒电路。每个存储体都具有核心电压源。功率门耦合到存储器组，用于对核心电压源进行充电并具有多个供电模式。银行唤醒电路耦合到电源门，用于选择多个功率模式之一，以在唤醒模式期间对存储体充电。银行唤醒电路在唤醒模式下感测核心电压源。存储体唤醒电路根据感测到的存储体的核心电压电源对存储体串行充电。

20. 发明申请

US20160148689A1 Sense Amplifier for Single-ended Sensing 有权
标题翻译：用于单端感测的感应放大器
公开(公告)号：US20160148689A1
公开(公告)日：2016-05-26
申请号：US14939782
申请日：2015-11-12
申请人： Invecas, Inc.
发明人： John Edward Barth, JR.
IPC分类号： G11C15/04
CPC分类号： G11C7/067 , G11C7/08 , G11C15/04
摘要： A single ended line sense amplifier having an input coupled to a single ended line having a near end and a far end device comprises a plurality of nFET stacks coupled between the near end of the single ended line and the far end of the single ended line, a single ended line comparator coupled to the near end of the single ended line configured to compare a voltage at the near end of the single ended line to provide a logic state output, and a charge transistor coupled to the single ended line at a point that is between the near end of the single ended line and the far end of the single ended line to shift occurrence of snap back from strong charging of the single ended line.
摘要翻译：具有耦合到具有近端和远端装置的单端线的输入的单端线读出放大器包括耦合在单端线的近端和单端线的远端之间的多个nFET堆叠，耦合到单端线路的近端的单端比较器比较器，被配置为比较单端线路近端处的电压以提供逻辑状态输出;以及电荷晶体管，其在位于单端线的近端和单端线的远端之间，从而使单端线的强充电发生跳变。

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