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1. 发明申请

US20190028090A1 Duty Cycle Detection 审中-公开
公开(公告)号：US20190028090A1
公开(公告)日：2019-01-24
申请号：US15654595
申请日：2017-07-19
申请人： Invecas, Inc.
发明人： Venkata N.S.N. Rao , Majid Jalali Far , Prasad Chalasani , Aram Martirosyan
IPC分类号： H03K3/017 , H03K5/156 , G11C7/22 , H03K9/08
CPC分类号： H03K3/017 , G11C7/222 , H03K5/1565 , H03K9/08 , H03K19/09429 , H03K19/1733
摘要： A pulse-width-to-voltage (“PWV”) converter, comprises: a switch, a capacitor, a current source, and a current sink. The switch is operable by a signal. The current source, the current sink, and the switch are serially connected across a high voltage potential and a low voltage potential. An output node is coupled to a serial connection between the current source and the current sink. An end of the capacitor is coupled to the output node for converting a current into a control voltage indicative of a duty cycle of the signal.

2. 发明申请

US20180006656A1 Clock Alignment Scheme for Data Macros of DDR PHY 有权
公开(公告)号：US20180006656A1
公开(公告)日：2018-01-04
申请号：US15707205
申请日：2017-09-18
申请人： Invecas, Inc.
发明人： Narasimhan Vasudevan , Venkata N.S.N. Rao , Prasad Chalasani
IPC分类号： H03L7/081 , H03L7/083 , G11C11/4063 , H03L7/091 , G11C7/22
CPC分类号： H03L7/0818 , G11C7/222 , G11C11/4063 , G11C11/4076 , H03L7/0812 , H03L7/083 , H03L7/085 , H03L7/089 , H03L7/091
摘要： A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.

3. 发明授权

US09715907B1 Optimal data eye for improved Vref margin 有权
公开(公告)号：US09715907B1
公开(公告)日：2017-07-25
申请号：US15150334
申请日：2016-05-09
申请人： Invecas, Inc.
发明人： Venkata N. S. N. Rao , Ravindra Kantamani , Prasad Chalasani
IPC分类号： G11C7/22 , G11C11/4076 , G11C8/18 , G11C7/00 , G11C11/4096 , G11C5/06
CPC分类号： G06N99/005 , G11C5/063 , G11C7/00 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/10 , G11C29/36 , G11C2029/3602 , G11C2207/2254
摘要： An optimized method and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.

4. 发明授权

US09613700B1 TCAM field enable logic 有权
公开(公告)号：US09613700B1
公开(公告)日：2017-04-04
申请号：US15183591
申请日：2016-06-15
申请人： Invecas, Inc.
发明人： Harold Pilo , Gerald P. Pomichter , Michael Lee , John Edward Barth, Jr.
IPC分类号： G11C15/00 , G11C15/04 , H03K19/177 , H03K19/00
CPC分类号： G11C15/04 , H03K19/0013 , H03K19/1776
摘要： A content addressable memory (“CAM”) field enabling logic comprises fields and field enable logics. The fields each have local match lines and a corresponding field enable control for enabling the respective field. The field enable logics are serially connected. Each of the fields is coupled to a corresponding one of the field enable logics via the respective local match lines. The corresponding field enable control for each of the fields is coupled to the corresponding one of the field enable logic and to any ones of the field enable logics that come after the corresponding one of the field enable logic along the serially-connected field enable logics.

5. 发明授权

US09564183B2 Sense amplifier having a timing circuit for a presearch and a main search 有权
标题翻译：具有用于预搜索和主搜索的定时电路的感测放大器
公开(公告)号：US09564183B2
公开(公告)日：2017-02-07
申请号：US14934050
申请日：2015-11-05
申请人： Invecas, Inc.
发明人： John Edward Barth, Jr.
IPC分类号： G11C15/04 , G11C7/06 , G11C7/08
CPC分类号： G11C7/067 , G11C7/08 , G11C15/04
摘要： A line sense amplifier comprises: a presearch block, a main search block, and a timing circuit. The presearch block is coupled to a presearch line for sensing the presearch line. The main search block is coupled to a main line for sensing the main line. The timing circuit operates the presearch block and the main search block for charging and sensing of the presearch line and the main line. The timing circuit initiates the main search block to determine a match condition for the main line based on whether a match condition is determined for the presearch line.
摘要翻译：线检测放大器包括：预搜索块，主搜索块和定时电路。预调查块与预检线相连接，用于感应预调线。主搜索块耦合到用于感测主线的主线。定时电路操作预搜索块和主搜索块，用于对预调线和主线进行充电和感测。定时电路基于是否为预调查线确定匹配条件，启动主搜索块以确定主线的匹配条件。

6. 发明申请

US20160224450A1 Memory Built-In Self Test System 有权
标题翻译：内存自检系统
公开(公告)号：US20160224450A1
公开(公告)日：2016-08-04
申请号：US15012707
申请日：2016-02-01
申请人： Invecas, Inc.
发明人： Kevin W. Gorman , Thomas Chadwick , Nancy Pratt
IPC分类号： G06F11/27
CPC分类号： G06F11/263 , G11C29/14 , G11C29/16 , G11C2029/0401
摘要： A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.
摘要翻译：内存自检（“BIST”）系统包括：控制器; 耦合到一个或多个单个端口存储器的单个端口存储器引擎; 以及耦合到一个或多个非单一端口存储器的非单端口存储器引擎。控制器接收用于测试多种存储器类型的操作代码（“操作代码”）。控制器的输出耦合到单端口存储器引擎和非单端口存储器引擎的输入。控制器根据接收的操作码产生测试指令。单端口存储器引擎和非单端口存储器引擎解释测试指令以测试一个或多个单端口存储器和一个或多个非单端口存储器。

7. 发明授权

US10484218B2 PWM demodulation 有权
公开(公告)号：US10484218B2
公开(公告)日：2019-11-19
申请号：US15904139
申请日：2018-02-23
申请人： Invecas, Inc.
发明人： Siva Kumar Rapina , Saravana Kumar Durairaj
IPC分类号： H04W4/33 , H04L27/156 , H03K5/003 , H03K9/08
摘要： A receiver for demodulating a pulse width modulated (“PWM”) signal, comprises: a voltage level shifter for shifting the PWM signal to predefined transistor voltage levels; a half-rate PWM decoder for receiving the shifted PWM signal; and a 2-bit-to-N-bit deserializer. The half-rate PWM decoder comprises a first decoder core, a second decoder core, a controller, and a sampler and retiming circuit. The first decoder core and the second decoder core are configured to decode alternating periods of the shifted PWM signal. The controller is coupled to the first decoder core, the second decoder core, the sampler and retiming circuit. The retiming circuit is configured to receive clock signals from the controller and to output half-rate even data from the first decoder core and half-rate odd data from the second decoder core. Outputs of the retiming circuit and an output of the controller are coupled to inputs of the deserializer.

8. 发明授权

US10302509B2 Temperature sensing for integrated circuits 有权
公开(公告)号：US10302509B2
公开(公告)日：2019-05-28
申请号：US15432208
申请日：2017-02-14
申请人： Invecas, Inc.
发明人： Santosh Kumar Pandiri , Prasanth Kumar Krishna , Koushik De , Ankush Kumar Dubey
IPC分类号： G01K15/00 , G01K7/01
摘要： Temperature sensors for integrated circuits that use back-gate bias for low power operation. A temperature sensor can comprise a voltage-gate-source generator having sensing transistors; an Ibias generator; a back-gate bias generator; and a temperature read-out circuit. In a calibration mode, the temperature sensor determines a back-gate bias voltage and a resistor trimming code to be used during functional operation.

9. 发明申请

US20190072589A1 Digital Voltmeter 审中-公开
公开(公告)号：US20190072589A1
公开(公告)日：2019-03-07
申请号：US15698289
申请日：2017-09-07
申请人： Invecas, Inc.
发明人： William Loh , Venkata N.S.N. Rao , Prasad Chalasani
IPC分类号： G01R19/25 , G01R19/255 , G01R19/155 , G01R15/12 , G01R13/02
摘要： A digital voltmeter, where a number of clock pulses for a first ramp voltage to reach an input voltage is determined. Next, a number of clock pulses for a second ramp voltage to reach the input voltage is determined. One of the first and the second ramp voltages having a least number of clock pulses to reach the input voltage is determined. A determination is made for a number of clock pulses for the determined one of the first and the second ramp voltages to reach a reference voltage. A digital code is generated for the input voltage based on the determined number of clock pulses for reaching the reference voltage and the determined least number of clock pulses for reaching the input voltage.

10. 发明授权

US09954538B2 Clock alignment scheme for data macros of DDR PHY 有权
公开(公告)号：US09954538B2
公开(公告)日：2018-04-24
申请号：US15192594
申请日：2016-06-24
申请人： Invecas, Inc.
发明人： Narasimhan Vasudevan , Venkata N. S. N. Rao , Prasad Chalasani
IPC分类号： H03L7/06 , H03L7/081 , H03L7/083 , H03L7/091 , G11C11/4063 , G11C7/22
CPC分类号： H03L7/0818 , G11C7/222 , G11C11/4063 , G11C11/4076 , H03L7/0812 , H03L7/083 , H03L7/085 , H03L7/089 , H03L7/091
摘要： A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.

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