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11. 发明申请

US20120213009A1 NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20120213009A1
公开(公告)日：2012-08-23
申请号：US13398397
申请日：2012-02-16
申请人： Seiichi ARITOME , Hyun-Seung YOO , Sung-Jin WHANG
发明人： Seiichi ARITOME , Hyun-Seung YOO , Sung-Jin WHANG
IPC分类号： G11C16/14 , H01L29/788
CPC分类号： G11C16/14 , G11C16/0408 , H01L27/11556 , H01L27/11582
摘要： A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.
摘要翻译：非易失性存储器件包括从衬底垂直延伸的沟道，沿着沟道堆叠的多个存储单元; 连接到所述沟道的第一端部的源极区域和与所述沟道的第二端部连接的位线，其中与所述源极区域相邻的所述沟道的所述第一端部形成为未掺杂的半导体层或半导体层掺杂有P型杂质。

12. 发明授权

US08199572B2 Non-volatile memory with both single and multiple level cells 有权
标题翻译：具有单级和多级单元的非易失性存储器
公开(公告)号：US08199572B2
公开(公告)日：2012-06-12
申请号：US13186172
申请日：2011-07-19
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C5/04 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C2211/5641
摘要： Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells.
摘要翻译：存储器阵列和操作这样的存储器阵列的方法被描述为具有作为单电平单元操作的存储单元，该存储单元被插入并耦合到选择栅极和作为多电平存储单元操作的存储单元。在一些实施例中，存储器阵列被描述为包括与作为单级存储器单元操作的多个存储器单元和作为多级存储器单元操作的多个存储单元串联耦合的多个选择栅极，其中第一选择栅极为直接耦合到第一存储器单元，该第一存储器单元被操作为插入在第一选择栅极之间并耦合到第一选择栅极的单层存储器单元，以及作为多级存储单元操作的连续数量的存储单元。

13. 发明申请

US20120106260A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20120106260A1
公开(公告)日：2012-05-03
申请号：US13282029
申请日：2011-10-26
申请人： Seiichi ARITOME , Soo Jin Wi , Angelo Visconti , Mattia Robustelli
发明人： Seiichi ARITOME , Soo Jin Wi , Angelo Visconti , Mattia Robustelli
IPC分类号： G11C16/06
CPC分类号： G11C16/3459 , G11C16/06 , G11C16/3454 , G11C16/3468
摘要： A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.
摘要翻译：一种操作半导体存储器件的方法包括执行第一程序操作以提高存储单元的阈值电压，执行用于检测快速程序存储单元的程序验证操作，每个程序存储单元的阈值电压升高高于第一次验证电压通过使用目标验证电压和顺序地低于目标验证电压的第一子验证电压和第二子验证电压，从第二子验证电压或更低的次级验证电压进行第二子验证电压，并且在低于目标验证电压的存储单元的每个阈值电压的增量大于每个快速程序存储单元的阈值电压的增量。

14. 发明授权

US08163610B2 Fabrication of finned memory arrays 有权
标题翻译：翅片式存储器阵列的制造
公开(公告)号：US08163610B2
公开(公告)日：2012-04-24
申请号：US13117364
申请日：2011-05-27
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/11521 , H01L29/66818 , H01L29/66825 , H01L29/7851 , H01L29/7854 , H01L29/7881
摘要： Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched to reduce a width of the fins and to round an upper surface of the fins. A first dielectric layer is formed overlying the isotropically etched fins. A first conductive layer is formed overlying the first dielectric layer. A second dielectric layer is formed overlying the first conductive layer. A second conductive layer is formed overlying the second dielectric layer.
摘要翻译：提供了方法和装置。对于一个实施例，在基板中形成多个散热片，使得散热片从基板突出。在形成多个翅片之后，翅片被各向同性地蚀刻以减小散热片的宽度并绕散热片的上表面。形成覆盖各向同性蚀刻的散热片的第一电介质层。第一导电层形成在第一介电层上。形成覆盖在第一导电层上的第二电介质层。第二导电层形成在第二介电层上。

15. 发明授权

US08144519B2 Programming a flash memory device 有权
标题翻译：编程闪存设备
公开(公告)号：US08144519B2
公开(公告)日：2012-03-27
申请号：US12973110
申请日：2010-12-20
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/06
CPC分类号： G11C16/3454
摘要： An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is verified up to a maximum verify voltage. A second verify read operation is then performed after the program/verify operation. The second verify read operation uses a verify voltage that is substantially close to the maximum verify voltage used during the program/verify step.
摘要翻译：在每个编程脉冲之后执行初始验证读操作。验证电压从第一个字线的初始验证电压开始，并且每个被验证到最大验证电压的字线增加。然后在程序/验证操作之后执行第二验证读操作。第二次验证读取操作使用基本上接近程序/验证步骤期间使用的最大验证电压的验证电压。

16. 发明申请

US20120051139A1 REDUCING READ FAILURE IN A MEMORY DEVICE 有权
标题翻译：减少存储设备中的读取故障
公开(公告)号：US20120051139A1
公开(公告)日：2012-03-01
申请号：US13272336
申请日：2011-10-13
申请人： Seiichi ARITOME , Alessandro TORSI , Carlo MUSILLI
发明人： Seiichi ARITOME , Alessandro TORSI , Carlo MUSILLI
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.
摘要翻译：在读取操作期间通过增加通过串行存储单元的漏极电流来减少读取失败。在一个实施例中，当所选字线在存储器块阵列的漏极侧的预定距离内时，对未选择的字线使用更高的读通过电压来实现。如果所选字线更靠近源极侧，则使用较低的读通过电压。在另一个实施例中，更靠近存储器块阵列的漏极侧的字线上的单元被擦除到比剩余字线上的存储器单元更低的阈值电压。

17. 发明授权

US08120954B2 Method, apparatus, and system for erasing memory 有权
标题翻译：擦除存储器的方法，设备和系统
公开(公告)号：US08120954B2
公开(公告)日：2012-02-21
申请号：US12833562
申请日：2010-07-09
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C11/5635 , G11C16/0483 , G11C16/107 , G11C16/3404 , G11C16/3409
摘要： Methods, apparatus, and systems may operate to perform a pre-programming operation on a plurality of multiple level memory cells of a memory device. An example of applying such a pre-programming operation involves applying a series of voltage pulses to the plurality of multiple level memory cells, verifying a charge stored in the plurality of multiple level memory cells, and erasing the plurality of multiple level memory cells of the memory block based on a result from verifying the charge stored in the plurality of multiple level memory cells.
摘要翻译：方法，装置和系统可以操作以在存储器件的多个多级存储器单元上执行预编程操作。应用这样的预编程操作的示例包括将一系列电压脉冲施加到多个多级存储器单元，验证存储在多个多级存储器单元中的电荷，以及擦除多个多级存储器单元中的多个多级存储器单元存储块基于验证存储在多个多级存储器单元中的电荷的结果。

18. 发明授权

US08084802B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08084802B2
公开(公告)日：2011-12-27
申请号：US13025957
申请日：2011-02-11
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： H01L27/108 , H01L29/73
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
摘要翻译：选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。第一级导电层具有接触区域。第二级导电层的部分被去除，位于接触区域上方。在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

19. 发明授权

US07995391B2 Multiple select gates with non-volatile memory cells 有权
标题翻译：具有非易失性存储单元的多个选择门
公开(公告)号：US07995391B2
公开(公告)日：2011-08-09
申请号：US12868245
申请日：2010-08-25
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer.
摘要翻译：描述与非易失性存储器单元相关联的多个选择门。各种实施例包括多个选择栅极结构，工艺和操作及其对存储器件，模块和系统的适用性。在一个实施例中描述了存储器阵列。存储器阵列包括多个与多个非易失性存储器单元串联耦合的选择栅极。第一选择栅极包括电连接在一起的控制栅极和浮置栅极，第二选择栅极包括由电介质层电隔离的控制栅极和浮置栅极。

20. 发明授权

US07961517B2 Program and read trim setting 有权
标题翻译：编程和读取修剪设置
公开(公告)号：US07961517B2
公开(公告)日：2011-06-14
申请号：US12547218
申请日：2009-08-25
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/102 , G11C16/26
摘要： A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.
摘要翻译：用于在存储器件中设置修剪参数的方法和装置根据观察或测试的编程速度和可靠性提供分配给存储器件部分的多个修整设置。

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