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11. 发明申请

US20150309550A1 MOBILE TERMINAL AND DISPLAY PANEL DRIVER 有权
标题翻译：移动终端和显示面板驱动程序
公开(公告)号：US20150309550A1
公开(公告)日：2015-10-29
申请号：US14692851
申请日：2015-04-22
申请人： SYNAPTICS DISPLAY DEVICES GK
发明人： Masaru SHIRAKAMI , Teru YONEYAMA
IPC分类号： G06F1/30
CPC分类号： G06F1/30 , G09G3/3696 , G09G2330/02 , G09G2330/027 , G09G2330/04
摘要： A power circuit section generates a first logic power supply voltage and an analog power supply voltage to supply to a first power supply line and a second power supply line, respectively. A regulator steps the first logic power supply voltage down to generate a second logic power supply voltage and supplies the second logic power supply voltage to a third power supply line. A logic circuit controls A source line driving section and A gate line driving section in response to a decrease of a voltage of the first power supply line so that the charge stored in the display panel is discharged. A charge transporting path is configured to transport the charge from the second power supply line to a third power supply line in response to the decrease of the voltage of the first power supply line.
摘要翻译：电源电路部分产生第一逻辑电源电压和模拟电源电压，以分别提供给第一电源线和第二电源线。 A调节器将第一逻辑电源电压降低以产生第二逻辑电源电压，并将第二逻辑电源电压提供给第三电源线。逻辑电路响应于第一电源线的电压的降低而控制A源极线驱动部分和A栅极线驱动部分，使得存储在显示面板中的电荷被放电。电荷输送路径被配置为响应于第一电源线的电压的降低将电荷从第二电源线传送到第三电源线。

12. 发明申请

US20160293096A1 INTERNAL CLOCK SIGNAL CONTROL FOR DISPLAY DEVICE, DISPLAY DRIVER AND DISPLAY DEVICE SYSTEM 有权
标题翻译：用于显示装置，显示驱动器和显示装置系统的内部时钟信号控制
公开(公告)号：US20160293096A1
公开(公告)日：2016-10-06
申请号：US15078217
申请日：2016-03-23
申请人： Synaptics Display Devices GK
发明人： Keiji NOSE
IPC分类号： G09G3/20
CPC分类号： G09G3/2096 , G06F3/038 , G09G3/2092 , G09G5/008 , G09G2330/021 , G09G2370/08 , G09G2370/10 , H04L7/0012 , H04L7/0083 , H04N21/4305
摘要： A display device includes a display panel and a display driver driving the display panel. The display driver is connected to a host with a clock lane and at least one a data lane. The display driver includes: an interface circuit configured to receive an external clock signal from the host via the clock lane, receive a data signal from the host via the data lane, and output reception data transmitted over the data signal; a control circuit configured to output an internal clock signal synchronous with the external clock signal; and a drive circuitry configured to drive the display panel in response to image data included in the reception data in synchronization with the internal clock signal fed from the control circuit. The control circuit is configured to feed the internal clock signal in response to a type of a reception packet included in the reception data.
摘要翻译：显示装置包括显示面板和驱动显示面板的显示驱动器。显示驱动器连接到具有时钟通道和至少一个数据通道的主机。显示驱动器包括：接口电路，被配置为经由时钟通道从主机接收外部时钟信号，经由数据通道从主机接收数据信号，并输出通过数据信号发送的接收数据; 控制电路，被配置为输出与所述外部时钟信号同步的内部时钟信号; 以及驱动电路，被配置为与从控制电路馈送的内部时钟信号同步地响应于包含在接收数据中的图像数据来驱动显示面板。控制电路被配置为响应于包含在接收数据中的接收分组的类型来馈送内部时钟信号。

13. 发明授权

US09454161B1 Semiconductor device and electronic apparatus 有权
标题翻译：半导体器件和电子设备
公开(公告)号：US09454161B1
公开(公告)日：2016-09-27
申请号：US15052547
申请日：2016-02-24
申请人： Synaptics Display Devices GK
发明人： Yoshinori Ura
IPC分类号： G11C8/08 , G11C8/10 , G05F1/10 , G09G3/36
CPC分类号： G05F1/10 , G09G3/3696 , G09G2330/027
摘要： Detection circuits cause a power supply circuit to start an initialization sequence by detecting abnormal behavior where an external power supply voltage is cut off, the power supply circuit generating a first internal power supply voltage from a first external power supply voltage and generating a second internal power supply voltage from a second external power supply voltage higher than the first external power supply voltage in terms of an absolute value, and an auxiliary amplifier that makes up for a drop in the first internal power supply voltage, using the second external power supply voltage as an operation power supply after detecting the abnormal behavior of the first external power supply voltage. A sample and hold circuit of a reference voltage of the auxiliary amplifier is configured in a hold state after detecting the abnormal behavior of the first external power supply voltage.
摘要翻译：检测电路使得电源电路通过检测外部电源电压被切断的异常行为来启动初始化序列，电源电路从第一外部电源电压产生第一内部电源电压并产生第二内部电源以比绝对值高的第一外部电源电压的第二外部电源电压供给电压，以及补偿第一内部电源电压下降的辅助放大器，使用第二外部电源电压作为在检测到第一外部电源电压的异常行为之后的操作电源。在检测到第一外部电源电压的异常行为之后，辅助放大器的参考电压的采样和保持电路被配置为保持状态。

14. 发明授权

US09444614B2 Dynamic power control for CDR 有权
标题翻译： CDR的动态功率控制
公开(公告)号：US09444614B2
公开(公告)日：2016-09-13
申请号：US14227469
申请日：2014-03-27
申请人： Synaptics Display Devices GK
发明人： Yude Liou
IPC分类号： G09G5/00 , H04L7/033 , G09G3/20 , H03L7/00 , H04L7/00
CPC分类号： H04L7/0331 , G09G3/2096 , G09G5/008 , H03L7/00 , H03L7/08 , H03L7/0802 , H04L7/0025 , H04L7/0337
摘要： An apparatus and method for dynamically controlling power of a device. In one embodiment, the apparatus includes a first circuit and a second circuit for generating a clock signal, wherein a frequency of the clock signal is dependent on a control voltage provided to the second circuit. A third circuit is coupled to receive the control voltage and is configured to adjust power consumed by the first circuit based on the control voltage.
摘要翻译：一种用于动态地控制设备功率的设备和方法。在一个实施例中，该装置包括用于产生时钟信号的第一电路和第二电路，其中时钟信号的频率取决于提供给第二电路的控制电压。第三电路被耦合以接收控制电压，并且被配置为基于控制电压来调整由第一电路消耗的功率。

15. 发明授权

US09437169B2 Touch panel control circuit and semiconductor integrated circuit using the same 有权
标题翻译：触摸屏控制电路和半导体集成电路采用相同的方式
公开(公告)号：US09437169B2
公开(公告)日：2016-09-06
申请号：US14567386
申请日：2014-12-11
申请人： Synaptics Display Devices GK
发明人： Takayuki Noto , Akihito Akai
IPC分类号： G06F3/044 , G09G5/18 , G06F3/041
CPC分类号： G09G5/18 , G06F3/0416 , G06F3/044
摘要： A touch panel control circuit includes a drive circuit that drives Y electrodes of a touch panel, and a detection circuit that is connected to X electrodes and detects a capacitance value of an intersection capacitor. The drive circuit applies a plurality of pulses to the Y electrodes in a predetermined period. The detection circuit includes a switched capacitor circuit capable of operating with respect to an input signal from the X electrodes in synchronization with the plurality of pulses, and an integration circuit that is connected to an output of the switched capacitor circuit and operates in synchronization with the pulses. The switched capacitor circuit is allowed to operate as a filter, and the switched capacitor circuit is set to have characteristics which have a maximum gain at a direct current and a frequency of a corresponding pulse and in which the gain is suppressed at a frequency therebetween.
摘要翻译：触摸面板控制电路包括驱动触摸面板的Y电极的驱动电路和与X电极连接并检测交叉电容器的电容值的检测电路。驱动电路在预定时间内向Y电极施加多个脉冲。检测电路包括能够与多个脉冲同步地来自X电极的输入信号进行操作的开关电容器电路，以及连接到开关电容器电路的输出并与其同步工作的积分电路脉冲。开关电容电路被允许作为滤波器工作，并且开关电容器电路被设置为具有在直流电流和相应脉冲的频率下具有最大增益的特性，并且其中增益被抑制在它们之间的频率处。

16. 发明授权

US09412755B2 Manufacturing method for semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US09412755B2
公开(公告)日：2016-08-09
申请号：US14572115
申请日：2014-12-16
申请人： Synaptics Display Devices GK
发明人： Hiroshi Ishida , Kazuhiko Sato
IPC分类号： H01L21/8234 , H01L27/115 , H01L21/28 , H01L29/66 , H01L29/792 , H01L29/49 , H01L21/265
CPC分类号： H01L27/11573 , H01L21/26586 , H01L21/28282 , H01L21/823462 , H01L29/4916 , H01L29/66537 , H01L29/792
摘要： In a manufacturing method for a semiconductor device provided with a MONOS-type FET for a non-volatile memory and high-voltage and low-voltage MOSFETs, a groove having a predetermined depth is formed in a region in which the high-voltage MOSFET on a semiconductor substrate is formed, and an oxide film serving as a gate insulating film of the high-voltage MOSFET is formed within the formed groove by thermal oxidation. Thereafter, a gate electrode film of the low-voltage MOSFET is formed on the entire surface of the semiconductor substrate. Thereafter, a region for the MONOS-type FET is opened, the semiconductor surface of the semiconductor substrate is exposed, and a first potential barrier film, a charge storage film, and a second potential barrier film are sequentially deposited, to thereby form a charge storage three-layer film. Agate electrode film of the MONOS-type FET is formed on the formed charge storage three-layer film.
摘要翻译：在具有用于非易失性存储器的MONOS型FET和高压和低压MOSFET的半导体器件的制造方法中，在高压MOSFET的区域中形成具有预定深度的沟槽形成半导体衬底，并且通过热氧化在形成的沟槽内形成用作高压MOSFET的栅极绝缘膜的氧化膜。此后，在半导体衬底的整个表面上形成低压MOSFET的栅极电极膜。此后，打开用于MONOS型FET的区域，半导体衬底的半导体表面被暴露，并且顺序地沉积第一势垒膜，电荷存储膜和第二势垒膜，从而形成电荷储存三层薄膜。在形成的电荷存储三层膜上形成MONOS型FET的玛瑙电极膜。

17. 发明授权

US09390471B1 Device and method for image scaling 有权
标题翻译：图像缩放的设备和方法
公开(公告)号：US09390471B1
公开(公告)日：2016-07-12
申请号：US14830249
申请日：2015-08-19
申请人： Synaptics Display Devices GK
发明人： Masao Orio , Hirobumi Furihata , Takashi Nose
IPC分类号： G06K9/32 , G06T3/40 , G06T5/50
CPC分类号： G06T3/4007
摘要： An image processing circuit includes a scaling processing section having interpolation coefficient inputs, an interpolation coefficient rearrangement section and an interpolation coefficient feeding section. The interpolation coefficient feeding section feeds first interpolation coefficients to the interpolation coefficient rearrangement section. The interpolation coefficient rearrangement section is configured to feed interpolation coefficients selected from the first interpolation coefficients and second interpolation coefficients obtained by subtracting the first interpolation coefficients from a predetermined value, respectively, to the respective interpolation coefficient inputs of the scaling processing section in response to coordinates of a target pixel of the output image. The scaling processing section is configured to generate pixel data of the target pixel of the output image by performing interpolation on the pixel data of pixels of the input image, using the interpolation coefficients fed to the interpolation coefficient inputs from the interpolation coefficient rearrangement section.
摘要翻译：图像处理电路包括具有插值系数输入的缩放处理部分，内插系数重排部分和内插系数提供部分。插补系数供给部将第一插值系数提供给插值系数重排部。内插系数重排部分被配置为将从第一内插系数中选择的内插系数和从预定值减去第一内插系数而获得的第二内插系数分别提供给缩放处理部分的各个内插系数输入，的输出图像的目标像素。缩放处理部被配置为通过使用从内插系数重排部输入的内插系数输入的内插系数对输入图像的像素的像素数据进行插值，来生成输出图像的目标像素的像素数据。

18. 发明授权

US09383857B2 Driver IC and display device 有权
标题翻译：驱动IC和显示设备
公开(公告)号：US09383857B2
公开(公告)日：2016-07-05
申请号：US14214963
申请日：2014-03-16
申请人： Synaptics Display Devices GK
发明人： Isao Munechika
IPC分类号： G06F3/041 , G09G5/00 , G09G5/12
CPC分类号： G06F3/0416 , G09G5/001 , G09G5/12
摘要： The driver IC includes: a control circuit operable to perform control for creating the timing of detection by a touch panel in a non-display drive period during which the action of a drive circuit remains stopped, and for creating a display drive period during which the drive circuit drives the display panel, and the non-display drive period; and a data RAM operable to hold display data of more than one display line, but smaller than one display frame in capacity. The control circuit performs control for alternately creating the display and non-display drive periods by repeating a memory-addressing operation for writing display data supplied from outside into the RAM and reading the display data from the RAM at a speed faster than the writing speed to provide the read data to the drive circuit two or more times in a period of one display frame according to a wraparound method.
摘要翻译：驱动器IC包括：控制电路，其可操作以执行控制，以在驱动电路的动作保持停止的非显示驱动时段中产生触摸面板的检测定时，并且用于创建显示驱动时段驱动电路驱动显示面板和非显示驱动周期; 以及数据RAM，其可操作以保持多于一个显示线的显示数据，但小于一个显示帧的容量。控制电路通过重复用于将从外部提供的显示数据写入RAM并且以比写入速度更快的速度从RAM读取显示数据的存储器寻址操作来执行用于交替地创建显示和非显示驱动周期的控制，以根据环绕方法在一个显示帧的周期内向驱动电路提供读取数据两次或更多次。

19. 发明授权

US09269672B2 Semiconductor integrated device for display drive 有权
标题翻译：半导体集成显示驱动器件
公开(公告)号：US09269672B2
公开(公告)日：2016-02-23
申请号：US14491995
申请日：2014-09-20
申请人： Synaptics Display Devices GK
发明人： Yasuhiro Kumagai , Masami Koketsu
IPC分类号： H01L23/544 , H01L23/522
CPC分类号： H01L23/544 , H01L23/5226 , H01L23/60 , H01L24/05 , H01L24/13 , H01L2223/54406 , H01L2223/5442 , H01L2223/54426 , H01L2223/54433 , H01L2223/54473 , H01L2224/05022 , H01L2224/05572 , H01L2224/13022 , H01L2224/13144 , H01L2924/0002 , H01L2924/00
摘要： In a display drive IC chip of an LCD or the like, an alignment mark is arranged in an alignment mark arrangement region on the main surface thereof, a dummy pattern is arranged on a lower layer, and an actual pattern is further arranged on the lower layer.
摘要翻译：在LCD等的显示驱动IC芯片中，在其主表面上的对准标记布置区域中布置有对准标记，在下层布置有虚设图案，并且实际图案进一步布置在下部层。

20. 发明授权

US09214354B2 Manufacturing method for semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US09214354B2
公开(公告)日：2015-12-15
申请号：US14572512
申请日：2014-12-16
申请人： Synaptics Display Devices GK
发明人： Hiroshi Ishida , Kazuhiko Sato
IPC分类号： H01L21/8242 , H01L21/306 , H01L27/115 , H01L21/762 , H01L21/28 , H01L29/66 , H01L21/8234 , H01L29/49 , H01L21/265
CPC分类号： H01L21/30625 , H01L21/26586 , H01L21/28282 , H01L21/76224 , H01L21/823462 , H01L27/11573 , H01L29/4916 , H01L29/66537 , H01L29/792
摘要： In a manufacturing method of sequentially forming a gate electrode film of the MOSFET, forming a gate electrode film of the non-volatile memory FET, patterning the gate electrode of the non-volatile memory FET, and patterning the gate electrode of the MOSFET, in order to form the MOSFET and the non-volatile memory FET on the same semiconductor substrate. The value of the product of S/L and H/L is specified in a case that the line of the gate electrode of the non-volatile memory FET is set to L, the space thereof is set to S, and the height thereof is set to H so that the thickness of a resist film on the gate electrode of the non-volatile memory FET which is formed in advance is set to a thickness which is not lost by etching for forming the gate electrode of the MOSFET.
摘要翻译：在顺序地形成MOSFET的栅电极膜的制造方法中，形成非易失性存储FET的栅电极膜，对非易失性存储FET的栅电极进行构图，并对MOSFET的栅极电极进行图案化，以便在相同的半导体衬底上形成MOSFET和非易失性存储器FET。在非易失性存储器FET的栅电极的线设定为L，其空间设定为S，其高度为S的情况下，规定S / L和H / L的乘积值设定为H，使得预先形成的非易失性存储FET的栅电极上的抗蚀剂膜的厚度被设定为不会通过用于形成MOSFET的栅电极的蚀刻而损失的厚度。

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