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11. 发明授权

US07669038B2 Method and apparatus for back to back issue of dependent instructions in an out of order issue queue 失效
标题翻译：方法和装置，用于在乱序问题队列中反向发布依赖指令
公开(公告)号：US07669038B2
公开(公告)日：2010-02-23
申请号：US12114010
申请日：2008-05-02
申请人： William Elton Burky , Raymond Cheung Yeung
发明人： William Elton Burky , Raymond Cheung Yeung
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838
摘要： A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following cycle. If an instruction was previously designated to issue during the particular cycle, one or more instructions in the queue are evaluated to determine if any of them are dependent on the designated instruction. For the evaluation, each instruction placed into the queue is accompanied by corresponding logic elements that provide destination to source compares for the instruction. In an embodiment comprising a method, the oldest ready instruction in the queue during a particular cycle is identified. When an instruction was previously designated to issue during the particular cycle, it is determined whether at least a first instruction in the queue complies with each condition in a set of conditions, the set including at least the conditions that the first instruction has a dependency on the designated instruction, and that the first instruction is older than the oldest ready instruction. The first instruction is selected for issue during the next following cycle only if the first instruction complies with each condition in the set.
摘要翻译：提供了一种用于在队列的特定周期期间评估出故障发送队列中的两个或更多个指令的方法，以在下一个后续周期中选择要发出的指令。如果先前指定在特定周期内发出指令，则会对队列中的一个或多个指令进行评估，以确定其中任何一个是否依赖于指定的指令。对于评估，放置到队列中的每条指令都伴随有相应的逻辑元素，为指令提供目标到源的比较。在包括方法的实施例中，识别在特定周期期间队列中最早的就绪指令。当先前指定在特定周期期间发出指令时，确定队列中的至少第一指令是否符合一组条件中的每个条件，该集合至少包括第一指令依赖于的条件指定的指令，并且第一条指令比最早的就绪指令更旧。仅当第一条指令符合该组中的每个条件时，才在下一个后续周期中选择第一条指令进行发布。

12. 发明申请

US20070282865A1 EFFICIENT DYNAMIC REGISTER FILE DESIGN FOR MULTIPLE SIMULTANEOUS BIT ENCODINGS 失效
标题翻译：高效的动态寄存器文件设计用于多个同时位的编码
公开(公告)号：US20070282865A1
公开(公告)日：2007-12-06
申请号：US11422422
申请日：2006-06-06
申请人： Vikas Agarwal , William Elton Burky , Zakaria Mahmood Khwaja
发明人： Vikas Agarwal , William Elton Burky , Zakaria Mahmood Khwaja
IPC分类号： G06F7/00
CPC分类号： G11C7/1006
摘要： The illustrative embodiment is a circuit and method for reversing a linked list of multiple nodes to produce a reversed linked list. The circuit includes a decoder for sequentially decoding multiple original input tags, which are associated with the nodes of the linked list, to produce decoded values, an array for storing the decoded values, and a circuit for reading the array to simultaneously generate the tags that are associated with the nodes of the reversed linked list, where separate encoders are not used.
摘要翻译：说明性实施例是用于反转多个节点的链表以产生反向链接列表的电路和方法。该电路包括用于顺序地解码与链表的节点相关联的多个原始输入标签以产生解码值的解码器，用于存储解码值的阵列，以及用于读取阵列以同时生成标签的电路与反向链表的节点相关联，其中不使用单独的编码器。

13. 发明授权

US07290261B2 Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor 有权
标题翻译：同时多线程（SMT）处理器中重命名寄存器重新分配的方法和逻辑设备
公开(公告)号：US07290261B2
公开(公告)日：2007-10-30
申请号：US10422651
申请日：2003-04-24
申请人： William Elton Burky , Bjorn Peter Christensen , Dung Quoc Nguyen , David A. Schroter , Albert Thomas Williams
发明人： William Elton Burky , Bjorn Peter Christensen , Dung Quoc Nguyen , David A. Schroter , Albert Thomas Williams
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/30076 , G06F9/30189 , G06F9/3836 , G06F9/384
摘要： A circuit and method provide rename register reallocation for simultaneous multi-threaded (SMT) processors that redistributes rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. The internal control logic then signals the resources to reallocate the resources. Rename resources are reallocated by directing an action at the rename mapper. When switching from SMT to ST mode, the mapper is directed to drop entries for the dying thread, but on a switch from ST to SMT mode, “dummy” instruction group dispatch indications are sent to the mapper that indicate use of all architected registers for each thread.
摘要翻译：电路和方法为同时多线程（SMT）处理器提供重命名寄存器重新分配，该处理器在单线程（ST）执行期间的一个线程和多线程执行期间的多个线程之间重新分配重命名（映射）资源。处理器接收指定从单线程转换到多线程模式或反之亦然的指令，并停止在处理器上执行的所有线程的执行。内部控制逻辑然后发出资源重新分配资源。重命名资源通过在重命名映射器处指示一个动作来重新分配。当从SMT切换到ST模式时，映射器被定向到垂死线程的条目，但是在从ST到SMT模式的切换中，将“伪”指令组分派指示发送到映射器，指示使用所有架构的寄存器每个线程。

14. 发明授权

US07155600B2 Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processor 失效
标题翻译：用于在同时多线程（SMT）处理器中在单线程和多线程执行状态之间切换的方法和逻辑设备
公开(公告)号：US07155600B2
公开(公告)日：2006-12-26
申请号：US10422648
申请日：2003-04-24
申请人： William Elton Burky , Michael Stephen Floyd , Ronald Nick Kalla , Balaram Sinharoy
发明人： William Elton Burky , Michael Stephen Floyd , Ronald Nick Kalla , Balaram Sinharoy
IPC分类号： G06F15/00 , G06F15/76 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/485
摘要： A method and logical apparatus for switching between single-threaded and multi-threaded execution states within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching between single-threaded and multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. Internal control logic controls a sequence of events that ends instruction prefetching, dispatch of new instructions, interrupt processing and maintenance operations and waits for operation of the processor to complete for instructions that are in process. Then, the logic determines one or more threads to start in conformity with a thread enable state specifying the enable state of multiple threads and reallocates various resources, dividing them between threads if multiple threads are specified for further execution (multi-threaded mode) or allocating substantially all of the resources to a single thread if further execution is specified as single-threaded mode. The processor then starts execution of the remaining enabled threads.
摘要翻译：用于在同时多线程（SMT）处理器中的单线程和多线程执行状态之间切换的方法和逻辑设备提供了在单线程和多线程执行之间进行切换的机制。处理器接收指定从单线程转换到多线程模式或反之亦然的指令，并停止在处理器上执行的所有线程的执行。内部控制逻辑控制结束指令预取，调度新指令，中断处理和维护操作的事件序列，并等待处理器的操作完成以处理正在进行的指令。然后，逻辑根据指定多个线程的使能状态的线程使能状态确定一个或多个线程，以重新分配各种资源，如果多个线程被指定用于进一步执行（多线程模式）或分配如果进一步执行被指定为单线程模式，则基本上所有的资源到单个线程。然后，处理器开始执行剩余的已启用线程。

15. 发明授权

US06275918B1 Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold 失效
标题翻译：从增加访问指示符阈值的数量获取历史表信息中的载入目标操作数预取地址
公开(公告)号：US06275918B1
公开(公告)日：2001-08-14
申请号：US09268307
申请日：1999-03-16
申请人： William Elton Burky , Peter Steven Lenk , Dung Quoc Nguyen , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
发明人： William Elton Burky , Peter Steven Lenk , Dung Quoc Nguyen , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
IPC分类号： G06F934
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832
摘要： A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based on the status of a validity bit contained in the entry. If the validity bit is set and the addresses match, an indicator field within the entry is checked to see if it is equal to or greater than a threshold level. When the indicator field is greater than the threshold level, a target operand address is pre-fetched based on stride and direction.
摘要翻译：公开了一种利用预取历史表改善数据处理系统中的预取精度的方法和系统。该方法基于条目中包含的有效位的状态，将指令地址的一部分与位于预取历史表中的条目的地址进行比较。如果有效位被设置并且地址匹配，则检查条目内的指示符字段以查看其是否等于或大于阈值级别。当指示符字段大于阈值电平时，将根据步幅和方向预取目标操作数地址。

16. 发明授权

US08108655B2 Selecting fixed-point instructions to issue on load-store unit 失效
标题翻译：选择在加载存储单元上发出的定点指令
公开(公告)号：US08108655B2
公开(公告)日：2012-01-31
申请号：US12410073
申请日：2009-03-24
申请人： Christopher Michael Abernathy , James Wilson Bishop , Mary Douglass Brown , William Elton Burky , Robert Allen Cordes , Hung Qui Le , Dung Quoc Nguyen , Todd Alan Venton
发明人： Christopher Michael Abernathy , James Wilson Bishop , Mary Douglass Brown , William Elton Burky , Robert Allen Cordes , Hung Qui Le , Dung Quoc Nguyen , Todd Alan Venton
IPC分类号： G06F9/302 , G06F9/312
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3885
摘要： Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In turn, the issue logic determines that the unified payload does not include a load-store instruction that is ready to issue. As a result, the issue logic issues the simple fixed point instruction to the load-store execution unit in response to determining that the simple fixed point instruction is ready to issue and determining that the unified payload does not include a load-store instruction that is ready to issue.
摘要翻译：问题逻辑标识一个简单的固定点指令，包含在一个准备发布的统一有效载荷中。简单的固定点指令是一种可由固定点执行单元和加载存储执行单元执行的指令。反过来，问题逻辑确定统一有效载荷不包括准备发布的加载存储指令。结果，响应于确定简单的固定点指令准备发出并且确定统一的有效载荷不包括加载存储指令，问题逻辑将简单的固定点指令发布到加载存储执行单元准备发行。

17. 发明授权

US08086826B2 Dependency tracking for enabling successive processor instructions to issue 有权
标题翻译：用于启用连续处理器指令发布的依赖性跟踪
公开(公告)号：US08086826B2
公开(公告)日：2011-12-27
申请号：US12409934
申请日：2009-03-24
申请人： Mary Douglass Brown , William Elton Burky , Dung Quoc Nguyen , Balaram Sinharoy
发明人： Mary Douglass Brown , William Elton Burky , Dung Quoc Nguyen , Balaram Sinharoy
IPC分类号： G06F9/38 , G06F9/52
CPC分类号： G06F9/3814 , G06F9/3838
摘要： An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions along with relative instruction to instruction dependency information. A mapper maps queue position data for instructions that dispatch to issue queue locations within the IU. The IU may test an issuing producer instruction against consumer instructions in the IU for queue position (QPOS) and register tag (RTAG) matches. A matching consumer instruction may issue in a successive manner in the case of a queue position match or in a next processor cycle in the case of a register tag match.
摘要翻译：信息处理系统包括具有发布单元（IU）的处理器，该单元可对连续指令发布操作执行指令依赖性跟踪。 IU保持非移位问题队列（NSIQ）和移位发送队列（SIQ）指令以及与指令依赖信息的相关指令。映射器映射队列位置数据，用于发送在IU内发出队列位置的指令。 IU可以根据IU中的消费者指令测试发出生产者指令的队列位置（QPOS）和注册标签（RTAG）匹配。在队列位置匹配的情况下，或者在注册标签匹配的情况下，在下一个处理器周期中，匹配的消费者指令可以以连续的方式发布。

18. 发明申请

US20100250901A1 Selecting Fixed-Point Instructions to Issue on Load-Store Unit 失效
标题翻译：选择加载存储单元发出的定点指令
公开(公告)号：US20100250901A1
公开(公告)日：2010-09-30
申请号：US12410073
申请日：2009-03-24
申请人： Christopher Michael Abernathy , James Wilson Bishop , Mary Douglass Brown , William Elton Burky , Robert Allen Cordes , Hung Qui Le , Dung Quoc Nguyen , Todd Alan Venton
发明人： Christopher Michael Abernathy , James Wilson Bishop , Mary Douglass Brown , William Elton Burky , Robert Allen Cordes , Hung Qui Le , Dung Quoc Nguyen , Todd Alan Venton
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3885
摘要： Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In turn, the issue logic determines that the unified payload does not include a load-store instruction that is ready to issue. As a result, the issue logic issues the simple fixed point instruction to the load-store execution unit in response to determining that the simple fixed point instruction is ready to issue and determining that the unified payload does not include a load-store instruction that is ready to issue.
摘要翻译：问题逻辑标识一个简单的固定点指令，包含在一个准备发布的统一有效载荷中。简单的固定点指令是一种可由固定点执行单元和加载存储执行单元执行的指令。反过来，问题逻辑确定统一有效载荷不包括准备发布的加载存储指令。结果，响应于确定简单的固定点指令准备发出并且确定统一的有效载荷不包括加载存储指令，问题逻辑将简单的固定点指令发布到加载存储执行单元准备发行。

19. 发明授权

US07536395B2 Efficient dynamic register file design for multiple simultaneous bit encodings 失效
标题翻译：用于多个同时位编码的高效动态寄存器文件设计
公开(公告)号：US07536395B2
公开(公告)日：2009-05-19
申请号：US11422422
申请日：2006-06-06
申请人： Vikas Agarwal , William Elton Burky , Zakaria Mahmood Khwaja
发明人： Vikas Agarwal , William Elton Burky , Zakaria Mahmood Khwaja
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G11C7/1006
摘要： The illustrative embodiment is a circuit and method for reversing a linked list of multiple nodes to produce a reversed linked list. The circuit includes a decoder for sequentially decoding multiple original input tags, which are associated with the nodes of the linked list, to produce decoded values, an array for storing the decoded values, and a circuit for reading the array to simultaneously generate the tags that are associated with the nodes of the reversed linked list, where separate encoders are not used.
摘要翻译：说明性实施例是用于反转多个节点的链表以产生反向链接列表的电路和方法。该电路包括用于顺序地解码与链表的节点相关联的多个原始输入标签以产生解码值的解码器，用于存储解码值的阵列，以及用于读取阵列以同时生成标签的电路与反向链表的节点相关联，其中不使用单独的编码器。

20. 发明授权

US07015718B2 Register file apparatus and method for computing flush masks in a multi-threaded processing system 失效
标题翻译：用于在多线程处理系统中计算闪存掩码的注册文件装置和方法
公开(公告)号：US07015718B2
公开(公告)日：2006-03-21
申请号：US10422684
申请日：2003-04-21
申请人： William Elton Burky , Peter Juergen Klim
发明人： William Elton Burky , Peter Juergen Klim
IPC分类号： H03K19/177
CPC分类号： G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： A method and apparatus for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent from the diagonal where the column index is equal to the row index. Each cell has a vertical write enable and a horizontal write enable. When a row is written to validate that row's tag value, the is column having an index equal to the row selector is automatically reset (excepting the bit corresponding to the absent cell mentioned above). On a read of a row in the array, a wired-AND circuit provided at each column provides a bit field corresponding to other rows that have been written since a last reset of the row, which is a flush mask indicating newer tags and the selected tag. Each cell in the array has an output for each thread supported by the array, and the logic provides a flush mask output for each thread as well as a combined flush mask output that supports simultaneous access for all of the threads.
摘要翻译：用于在多线程处理系统中计算闪存掩码的方法和装置响应于多个刷新请求源而提供刷新结果的快速和低逻辑开销计算。刷新掩码寄存器文件由数组中的多个单元格实现，其中单元格不在对角线，其中列索引等于行索引。每个单元都具有垂直写入使能和水平写入使能。当一行被写入以验证该行的标签值时，具有等于行选择器的索引的列被自动复位（除了与上述缺少的单元格相对应的位）。在阵列中的一行读取中，每列提供的有线AND电路提供了与自行的最后一次复位以来写入的其他行相对应的位字段，该行是指示较新标记的刷新掩码，并且所选择的标签。数组中的每个单元格都具有数组支持的每个线程的输出，逻辑为每个线程提供了一个刷新掩码输出以及一个组合的刷新输出，支持所有线程的同时访问。

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