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11. 发明申请

US20120161859A1 INTERNAL SUPPLY VOLTAGE GENERATING CIRCUIT AND METHOD FOR GENERATING INTERNAL SUPPLY VOLTAGE 审中-公开
标题翻译：内部电源电压生成电路及内部电源电压的生成方法
公开(公告)号：US20120161859A1
公开(公告)日：2012-06-28
申请号：US13402528
申请日：2012-02-22
申请人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G05F3/02
CPC分类号： G05F1/56 , G11C5/145 , H03L7/0812 , H03L7/093
摘要： An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator, and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.
摘要翻译：内部电源电压产生电路包括：时钟比较器，被配置为将具有与参考电压电平相对应的时钟信息的第一时钟信号与具有对应于内部电源电压电平的时钟信息的第二时钟信号进行比较;控制信号发生器被配置为产生具有与时钟比较器的输出信号对应的电压电平的驱动控制电压，以及被配置为响应于驱动控制电压驱动内部电源电压的端子的驱动器。

12. 发明申请

US20120105119A1 INTEGRATED CIRCUIT 有权
标题翻译：集成电路
公开(公告)号：US20120105119A1
公开(公告)日：2012-05-03
申请号：US12981764
申请日：2010-12-30
申请人： Yong-Ju Kim , Seong-Jun Lee , Hae-Rang Choi , Jae-Min Jang
发明人： Yong-Ju Kim , Seong-Jun Lee , Hae-Rang Choi , Jae-Min Jang
IPC分类号： H03L7/06
CPC分类号： H03L7/0816
摘要： An integrated circuit includes a delay locked loop configured to delay a reference clock signal by a delay time for delay locking and generate a delay locked clock signal, a clock transmission circuit configured to transmit the delay locked clock signal in response to a clock transmission signal, a duty correction circuit configured to perform duty correction operation on an output clock signal of the clock transmission circuit, and a clock transmission signal generation circuit configured to generate the clock transmission signal in response to a command and burst length information.
摘要翻译：一种集成电路包括：延迟锁定环路，被配置为延迟参考时钟信号延迟锁定的延迟时间，并产生延迟锁定时钟信号;时钟传输电路，被配置为响应于时钟传输信号传输延迟锁定时钟信号; 配置为对时钟发送电路的输出时钟信号进行占空比校正操作的占空比校正电路，以及响应于命令和突发长度信息而生成时钟发送信号的时钟发送信号生成电路。

13. 发明授权

US08149953B2 Data receiver of semiconductor integrated circuit 失效
标题翻译：半导体集成电路数据接收器
公开(公告)号：US08149953B2
公开(公告)日：2012-04-03
申请号：US12177829
申请日：2008-07-22
申请人： Hyung-Soo Kim , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
发明人： Hyung-Soo Kim , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： H03K9/00
CPC分类号： H03K19/09425
摘要： A semiconductor integrated circuit equipped with an equalizer which has a circuit structure simpler than that of a related equalizer according to an FFE scheme or a DFE scheme and is capable of preventing a noise component from being amplified. The data receiver includes a plurality of receiver units, wherein each receiver unit includes a plurality of level detectors which detect different levels, and an encoder, in which the level detectors receive data according to a clock signal having a predetermined phase difference and perform an amplification operation including an equalization function based on feedback data, thereby outputting an amplification signal, and wherein level detectors of one receiver unit receive an amplification signal, as the feedback data, from level detectors of another receiver unit that receives a first clock signal having a phase more advanced than a phase of a second clock signal received in one receiver unit.
摘要翻译：一种配备有均衡器的半导体集成电路，其具有比根据FFE方案或DFE方案的相关均衡器的电路结构简单的电路结构，并且能够防止噪声分量被放大。数据接收机包括多个接收机单元，其中每个接收机单元包括检测不同电平的多个电平检测器和编码器，其中电平检测器根据具有预定相位差的时钟信号接收数据并执行放大操作包括基于反馈数据的均衡功能，从而输出放大信号，并且其中一个接收器单元的电平检测器从另一接收器单元的电平检测器接收作为反馈数据的放大信号，该接收器单元接收具有相位的第一时钟信号比在一个接收机单元中接收的第二时钟信号的相位更先进。

14. 发明授权

US08144531B2 Latency control circuit, semiconductor memory device including the same, and method for controlling latency 失效
标题翻译：延迟控制电路，包括其的半导体存储器件以及用于控制延迟的方法
公开(公告)号：US08144531B2
公开(公告)日：2012-03-27
申请号：US12633387
申请日：2009-12-08
申请人： Hae-Rang Choi , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hae-Rang Choi , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C2207/2272
摘要： A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information.
摘要翻译：延迟控制电路包括路径计算器，被配置为计算输入信号在芯片内经过的路径的延迟值，并输出延迟值作为路径信息;延迟值计算器，被配置为输出表示延迟值的延迟信息用于基于所述输入信号和所述路径信息的等待时间值延迟所述输入信号;以及延迟器，被配置为将所述输入信号延迟与所述延迟信息相对应的延迟。

15. 发明授权

US08120442B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08120442B2
公开(公告)日：2012-02-21
申请号：US12266787
申请日：2008-11-07
申请人： Ji-Wang Lee , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi
发明人： Ji-Wang Lee , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi
IPC分类号： H04B3/04
CPC分类号： H04B3/32 , H03K5/131 , H03K5/135 , H03K5/1534 , H03K2005/00071 , H04L25/0272 , H04L25/0286 , H04L25/029
摘要： A semiconductor device includes transmission lines for conveying signals and transition detectors, each of which checks whether a transmission signal on each of the plurality of transmission lines is transited. If the signal is transited, its transition shape is detected. A signal mode determining unit determines signal transmission modes between adjacent transmission lines in response to output signals from the plurality of transition detectors. Delay units are coupled to the respective transmission lines for adjusting transmission delays of the transmission signals depending on corresponding output signal from the signal mode determining units.
摘要翻译：半导体器件包括用于传送信号的传输线和转换检测器，每个传输线检查多条传输线中的每条传输线上的传输信号是否被转换。如果信号被转移，则检测其转换形状。信号模式确定单元响应于来自多个转换检测器的输出信号来确定相邻传输线之间的信号传输模式。延迟单元耦合到各个传输线，用于根据来自信号模式确定单元的相应输出信号来调整传输信号的传输延迟。

16. 发明申请

US20110309867A1 PHASE LOCKED LOOP 有权
标题翻译：相位锁定环
公开(公告)号：US20110309867A1
公开(公告)日：2011-12-22
申请号：US12916901
申请日：2010-11-01
申请人： Hae-Rang CHOI , Yong-Ju Kim , Jae-Min Jang
发明人： Hae-Rang CHOI , Yong-Ju Kim , Jae-Min Jang
IPC分类号： H03L7/08
CPC分类号： H03L7/14 , H03L7/113
摘要： A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.
摘要翻译：锁相环包括相位检测器，被配置为将输入时钟的相位与反馈时钟的相位进行比较以产生相位比较结果，初始频率值提供器被配置为检测输入时钟的频率并提供频率检测结果，配置为基于相位比较结果和频率检测结果产生频率控制信号的控制器，以及响应于频率控制信号产生输出时钟的振荡器。

17. 发明授权

US08076964B2 Sampling circuit 有权
标题翻译：采样电路
公开(公告)号：US08076964B2
公开(公告)日：2011-12-13
申请号：US12630021
申请日：2009-12-03
申请人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03K3/00
CPC分类号： H03K3/356139 , G06F5/06 , H03K3/0375
摘要： A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.
摘要翻译：一种用于半导体器件的采样电路，包括：第一采样单元，被配置为与参考时钟信号同步地采样数据信号并输出第一输出信号;第二采样单元，被配置为与延迟数据信号同步采样参考时钟信号并输出第二输出信号;以及输出单元，被配置为组合第一和第二输出信号并输出采样数据信号。

18. 发明申请

US20110285419A1 SEMICONDUCTOR INTEGRATED CIRCUIT FOR GENERATING CLOCK SIGNALS 审中-公开
标题翻译：用于产生时钟信号的半导体集成电路
公开(公告)号：US20110285419A1
公开(公告)日：2011-11-24
申请号：US13204594
申请日：2011-08-05
申请人： Hyung Soo Kim , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang
发明人： Hyung Soo Kim , Yong Ju Kim , Jong Woon Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G01R29/26
摘要： A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference dock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.
摘要翻译：一种用于半导体集成电路的电压测量装置包括：第一延迟单元，被配置为延迟第一区域中的参考时钟;第二延迟单元，被配置为在第二区域中延迟参考基准;以及分析单元，被配置为分析电压差基于与由第一延迟单元和第二延迟单元产生的延迟时钟信号相关联的相位，区域之间的电平。

19. 发明授权

US07952394B2 Signal receiver circuit capable of improving area and power efficiency in semiconductor integrated circuits 有权
标题翻译：信号接收电路能够提高半导体集成电路的面积和功率效率
公开(公告)号：US07952394B2
公开(公告)日：2011-05-31
申请号：US12770706
申请日：2010-04-29
申请人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
发明人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H03K5/22
CPC分类号： H03K5/08 , H03K3/356139 , H03K3/356191 , H04L25/062
摘要： A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.
摘要翻译：信号接收器电路包括第一电平检测器，用于响应于一对第一参考信号偏移控制第一输出节点。第二级检测器偏移 - 响应于一对第二参考信号来控制第二输出节点。

20. 发明授权

US07948287B2 DLL circuit of semiconductor memory apparatus 有权
标题翻译：半导体存储装置的DLL电路
公开(公告)号：US07948287B2
公开(公告)日：2011-05-24
申请号：US11964824
申请日：2007-12-27
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Wong Song , Hyung Soo Kim , Tae Jin Hwang
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Hee Wong Song , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.
摘要翻译：一种用于半导体存储装置的DLL电路包括具有粗略延迟链的延迟线，该延迟线具有串联连接并被输入参考时钟信号的多个粗延迟器，以及多个精细延迟器，其接收输出时钟信号的输出时钟信号相应的粗延迟器和延迟控制部分，用于将粗延迟器中的最终粗延迟器的输出时钟信号的相位与参考时钟信号进行比较，并产生用于控制粗略延迟器的粗略控制信号，并用于比较输出时钟信号的相位输入与最终粗略延迟器的输出时钟信号作为精细反馈时钟信号的精细延迟器与参考时钟信号，并产生用于控制精细延迟器的精细控制信号。

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