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11. 发明授权

US09577641B2 Spin transfer torque based memory elements for programmable device arrays 有权
标题翻译：用于可编程器件阵列的基于转移转矩的存储元件
公开(公告)号：US09577641B2
公开(公告)日：2017-02-21
申请号：US15016260
申请日：2016-02-04
申请人： Intel Corporation
发明人： Arijit Raychowdhury , James W. Tschanz , Vivek De
IPC分类号： H03K19/177 , G11C11/16
CPC分类号： H03K19/17728 , G11C11/16 , H03K19/177
摘要： Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.
摘要翻译：这里公开了使用基于高密度旋转转矩（STT）的存储器元件的半导体器件阵列，诸如现场可编程门阵列（FPGA）和复数可编程逻辑阵列（CPLAs）。基于STT的存储器元件可以是独立的FPGA / CPLAs，或者可以嵌入在微处理器和/或数字信号处理（DSP）片上系统（SoC）中，以提供设计灵活性，以实现低功率，可扩展，安全和可重构硬件架构。由于配置存储在FPGA / CPLA裸片本身，所以每次在外部存储器上加载配置的需求都将在设备通电时被消除。除了即时启动，消除配置I / O流量导致节电和可能的引脚数减少。通过消除将配置数据存储在外部存储器中的需要，安全性大大提高。

12. 发明申请

US20160210192A1 RESILIENT REGISTER FILE CIRCUIT FOR DYNAMIC VARIATION TOLERANCE AND METHOD OF OPERATING THE SAME 有权
标题翻译：用于动态变化公差的弹性寄存器文件电路及其操作方法
公开(公告)号：US20160210192A1
公开(公告)日：2016-07-21
申请号：US15083122
申请日：2016-03-28
申请人： INTEL CORPORATION
发明人： Jaydeep P. Kulkarni , Keith A. Bowman , James W. Tschanz , Vivek K. De
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/1068 , G06F9/30141 , G06F9/3861 , G06F11/0751 , G06F11/1008 , G11C7/18 , G11C29/42 , G11C29/52
摘要： The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
摘要翻译：所公开的系统和方法检测并校正由于减少或消除CPU的电源电压保护带和/或频率保护带而可能发生的寄存器文件读取路径错误，从而提高了系统的总体能量效率。

13. 发明授权

US09373395B1 Apparatus to reduce retention failure in complementary resistive memory 有权
标题翻译：减少互补电阻记忆体保留失效的装置
公开(公告)号：US09373395B1
公开(公告)日：2016-06-21
申请号：US14638942
申请日：2015-03-04
申请人： Intel Corporation
发明人： Charles Augustine , Wei Wu , Shigeki Tomishima , Shih-Lien L. Liu , James W. Tschanz
IPC分类号： G11C13/00 , G11C11/419
CPC分类号： G11C13/0069 , G11C7/1006 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0021 , G11C13/0033 , G11C13/004 , G11C2013/0042 , G11C2213/79 , G11C2213/82
摘要： Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node.
摘要翻译：描述了一种装置，其包括：互补电阻存储器位单元; 以及耦合到所述互补电阻存储器位单元的读出放大器，其中所述读出放大器包括：第一输出节点; 以及第一晶体管，其可操作以在所述第一输出节点上产生确定性输出。

14. 发明申请

US20160173092A1 CURRENT STEERING LEVEL SHIFTER 有权
标题翻译：电流转向水平仪
公开(公告)号：US20160173092A1
公开(公告)日：2016-06-16
申请号：US14569569
申请日：2014-12-12
申请人： Intel Corporation
发明人： Amit R. Trivedi , Jaydeep P. Kulkarni , Dinesh Somasekhar , Muhammad M. Khellah , Carlos Tokunaga , James W. Tschanz
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509
摘要： Described is an apparatus which comprises: a first power supply node to provide a first power supply; a second power supply node to provide a second power supply; a driver to operate on the first power supply, the driver to generate an output; and a receiver to operate on the second power supply, the receiver to receive the output from the driver and to generate a level-shifted output such that the receiver is operable to steer current from the second power supply to the first power supply.
摘要翻译：描述了一种装置，其包括：第一电源节点，用于提供第一电源; 第二电源节点，用于提供第二电源; 驱动器在第一电源上运行，驱动器产生输出; 以及接收器，用于在所述第二电源上操作，所述接收器接收来自所述驱动器的输出并产生电平移位输出，使得所述接收器可操作以将电流从所述第二电源转向所述第一电源。

15. 发明授权

US09830988B2 Apparatus to reduce retention failure in complementary resistive memory 有权
公开(公告)号：US09830988B2
公开(公告)日：2017-11-28
申请号：US15187646
申请日：2016-06-20
申请人： Intel Corporation
发明人： Charles Augustine , Wei Wu , Shigeki Tomishima , Shih-Lien L. Lu , James W. Tschanz
IPC分类号： G11C13/00 , G11C11/16 , G11C7/10
CPC分类号： G11C13/0069 , G11C7/1006 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0021 , G11C13/0033 , G11C13/004 , G11C2013/0042 , G11C2213/79 , G11C2213/82
摘要： Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node.

16. 发明授权

US09805790B2 Memory cell with retention using resistive memory 有权
公开(公告)号：US09805790B2
公开(公告)日：2017-10-31
申请号：US15025229
申请日：2013-12-05
申请人： Intel Corporation
发明人： Nathaniel J. August , Pulkit Jain , Stefan Rusu , Fatih Hamzaoglu , Rangharajan Venkatesan , Muhammad Khellah , Charles Augustine , Carlos Tokunaga , James W. Tschanz , Yih Wang
IPC分类号： G11C13/00 , G11C14/00 , G11C11/16
CPC分类号： G11C13/0061 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C13/0011 , G11C13/0014 , G11C14/0081 , G11C14/009
摘要： Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

17. 发明授权

US09772903B2 Resilient register file circuit for dynamic variation tolerance and method of operating the same 有权
公开(公告)号：US09772903B2
公开(公告)日：2017-09-26
申请号：US15083122
申请日：2016-03-28
申请人： INTEL CORPORATION
发明人： Jaydeep P. Kulkarni , Keith A. Bowman , James W. Tschanz , Vivek K. De
IPC分类号： G06F11/10 , G06F11/00 , G11C29/52 , G06F9/30 , G06F11/07 , G06F9/38 , G11C29/42 , G11C7/18
CPC分类号： G06F11/1068 , G06F9/30141 , G06F9/3861 , G06F11/0751 , G06F11/1008 , G11C7/18 , G11C29/42 , G11C29/52
摘要： The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.

18. 发明授权

US09563263B2 Graphics processor sub-domain voltage regulation 有权
标题翻译：图形处理器子域电压调节
公开(公告)号：US09563263B2
公开(公告)日：2017-02-07
申请号：US14134598
申请日：2013-12-19
申请人： Intel Corporation
发明人： Subramaniam Maiyuran , Muhammad M. Khellah , James W. Tschanz
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/324 , G06F1/3243 , G06F1/3287 , Y02D10/126 , Y02D10/152 , Y02D10/171 , Y02D10/172
摘要： Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.
摘要翻译：由相同的电压域电源轨提供的处理器子域的电压调节。电压域内的某些逻辑单元的电压可以相对于电压域的其它逻辑单元减小，从而在高功率下减少空闲时间。在一个实施例中，第一电压调节子域包括至少一个执行单元（EU），而第二电压调节子域包括至少一个纹理采样器，以提供设置图形核心功率性能点超出调制的灵活性通过电源域（门控）控制有效的欧盟计数。在实施例中，子域电压由用于快速电压切换的片上DLDO调节。时钟频率和子域电压可能比电压域电源轨的电压更快，从而允许更精细的电源管理，可以响应欧盟的工作负载需求。

19. 发明授权

US09520877B2 Apparatus and method for detecting or repairing minimum delay errors 有权
标题翻译：用于检测或修复最小延迟误差的装置和方法
公开(公告)号：US09520877B2
公开(公告)日：2016-12-13
申请号：US14572031
申请日：2014-12-16
申请人： Intel Corporation
发明人： Pascal A. Meinerzhagen , Sandip Kundu , James W. Tschanz , Vivek K. De
IPC分类号： H03L7/00 , H03K19/003 , H03K5/26
CPC分类号： H03K19/00323 , H03K5/26
摘要： Described are apparatuses and methods for detecting or repairing minimum-delay errors. The apparatus may include a minimum-delay error detector (MDED) to receive a clock signal and a data path signal and to detect a minimum-delay error (MDE) in the data path based on the received data path signal and the clock signal. The MDE may be repaired by adjusting one or more regional clock buffers coupled to the MDED. Further, the apparatus may include minimum-delay path replicas (MDPRs) used for detecting and repairing MDEs during normal system operations. Other embodiments may be described and/or claimed.
摘要翻译：描述了用于检测或修复最小延迟误差的装置和方法。该装置可以包括用于接收时钟信号和数据路径信号的最小延迟误差检测器（MDED），并且基于所接收的数据路径信号和时钟信号来检测数据路径中的最小延迟误差（MDE）。可以通过调整耦合到MDED的一个或多个区域时钟缓冲器来修复MDE。此外，该装置可以包括用于在正常系统操作期间检测和修复MDE的最小延迟路径副本（MDPR）。可以描述和/或要求保护其他实施例。

20. 发明申请

US20160294394A1 VOLTAGE LEVEL SHIFTER CIRCUIT 审中-公开
标题翻译：电压水平更换电路
公开(公告)号：US20160294394A1
公开(公告)日：2016-10-06
申请号：US15182486
申请日：2016-06-14
申请人： INTEL CORPORATION
发明人： Amit R. Trivedi , Jaydeep P. Kulkarni , Carlos Tokunaga , Muhammad M. Khellah , James W. Tschanz
IPC分类号： H03K19/0185
CPC分类号： H03K19/018521 , H03K3/356113
摘要： Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.
摘要翻译：实施例包括用于在低电压域和高电压域之间电压移位数据信号的装置，方法和系统。在实施例中，电压电平移位器电路可以包括自适应保持器电路，增强的可中断电源电路和/或电容升压电路，以减小由电压电平移位器电路支持的低电压域的最小电压。可以描述和要求保护其他实施例。

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