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11. 发明授权

US09257151B2 Printed-circuit board supporting memory systems with multiple data-bus configurations 有权
标题翻译：支持具有多种数据总线配置的存储系统的印刷电路板
公开(公告)号：US09257151B2
公开(公告)日：2016-02-09
申请号：US14306304
申请日：2014-06-17
申请人： Rambus Inc.
发明人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F12/00 , G11C5/04 , G06F12/06 , G06F12/04 , G06F13/16 , G11C5/02 , G11C5/06 , G11C7/10 , G11C11/408 , G11C11/4097 , H05K1/14 , G11C8/06 , H05K1/11
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described is a printed-circuit board (PCB) that supports memory systems in which the memory core organization changes with device width. The PCB includes a memory-controller mounting location and module connectors to receive respective memory modules. Each module connector connects directly to the controller mounting location via a respective set of system data lines that does not connect to any other module connector. System data lines also extend directly between module connectors to support memory configurations with different numbers of modules. The memory systems support one memory module of a wide data width or multiple memory modules of narrower data widths. The number of physical memory banks accessed reduces with device data width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.
摘要翻译：描述了支持存储器系统的印刷电路板（PCB），其中存储器核心组织随设备宽度而变化。 PCB包括存储器控制器安装位置和模块连接器以接收相应的存储器模块。每个模块连接器通过不连接到任何其他模块连接器的相应的一组系统数据线直接连接到控制器安装位置。系统数据线也直接在模块连接器之间扩展，以支持具有不同数量模块的存储器配置。存储器系统支持宽数据宽度的一个存储器模块或较窄数据宽度的多个存储器模块。访问的物理存储器组的数量随设备数据宽度而减少，导致相对较窄的存储器配置的功率消耗减少。增加用于窄内存宽度的逻辑内存库的数量可以减少存储体冲突的可能性，从而提高速度性能。

12. 发明授权

US09160466B2 Periodic calibration for communication channels by drift tracking 有权
标题翻译：通过漂移跟踪定期通信通道
公开(公告)号：US09160466B2
公开(公告)日：2015-10-13
申请号：US14535006
申请日：2014-11-06
申请人： Rambus Inc.
发明人： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
IPC分类号： H04B17/00 , H04B3/46 , H04L7/00 , H04L7/04 , H04L7/10 , H04L27/00 , H04Q1/20
CPC分类号： H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
摘要翻译：提供执行第一校准序列的方法和系统，例如在系统初始化时，建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量在参数中漂移，并根据测量的漂移更新操作值。与第一校准序列相比，第二校准序列使用较少的通信信道资源。在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2N-1位的伪随机比特序列，其中N等于或大于而第二校准序列使用短校准模式，例如小于16字节的固定代码，例如短至2字节长。

13. 发明申请

US20150063433A1 Periodic Calibration For Communication Channels By Drift Tracking 有权
公开(公告)号：US20150063433A1
公开(公告)日：2015-03-05
申请号：US14535006
申请日：2014-11-06
申请人： Rambus Inc.
发明人： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
IPC分类号： H04B17/00
CPC分类号： H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

14. 发明授权

US08929424B2 Periodic calibration for communication channels by drift tracking 有权
公开(公告)号：US08929424B2
公开(公告)日：2015-01-06
申请号：US14145966
申请日：2014-01-01
申请人： Rambus Inc.
发明人： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
IPC分类号： H04B3/46 , H04B17/00 , H04L7/00 , H04L7/04 , H04L27/00 , H04L7/10 , H04Q1/20
CPC分类号： H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

15. 发明申请

US20140192940A1 COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS 有权
标题翻译：通信通道校准条件
公开(公告)号：US20140192940A1
公开(公告)日：2014-07-10
申请号：US14201778
申请日：2014-03-07
申请人： Rambus Inc.
发明人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel
IPC分类号： H04L7/00
CPC分类号： H04L7/0016 , G11C7/04 , G11C2207/2254 , H04L7/0087 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/0292 , H04L25/12
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
摘要翻译：方法和系统提供在通信信道的正常操作期间不时地执行校准周期。校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。使用第二组件上的接收器从通信链路接收校准模式。响应于所接收的校准模式来确定通信信道的参数的校准值。校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，以及将这些校准模式重新发送回第一组件以用于调整第一组件上的通道的参数。

16. 发明申请

US20130305079A1 Memory Component that Samples Command/Address Signals in Response to Both Edges of a Clock Signal 有权
标题翻译：采样命令/地址信号响应时钟信号的两个边沿的存储器组件
公开(公告)号：US20130305079A1
公开(公告)日：2013-11-14
申请号：US13923656
申请日：2013-06-21
申请人： Rambus Inc.
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F1/10
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory component has a signaling interface, data input/output (I/O) circuitry and command/address (CA) circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component.
摘要翻译：存储器组件具有信令接口，数据输入/输出（I / O）电路和命令/地址（CA）电路。信令接口包括片上终端数据I / O和未终止的CA输入。数据I / O电路专用于以由选通信号定时的数据I / O对写入数据位进行采样，并发送由第一时钟信号定时的读取数据位，每个写入和读取数据位对于位有效时间在数据I / O。 CA电路响应于第二时钟信号的上升沿和下降沿转换在CA输入端采样CA信号，CA信号指示要在存储器组件内执行的读和写操作。

17. 发明申请

US20130194879A1 Early Read After Write Operation Memory Device, System And Method 有权
标题翻译：写操作后的早期读取存储器件，系统和方法
公开(公告)号：US20130194879A1
公开(公告)日：2013-08-01
申请号：US13712842
申请日：2012-12-12
申请人： Rambus Inc.
发明人： Richard E. Perego , Frederick A. Ware
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C2207/2281 , G11C2207/229
摘要： A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.
摘要翻译：根据本发明的实施例，提供了在一个或多个写入操作之后允许早期读取操作的存储器件，系统和方法。存储器件包括用于提供第一写入地址，第一写入数据和读取地址的接口。存储器核心耦合到接口并且包括具有第一数据路径和第一地址路径的第一存储器部分和具有第二数据路径和第二地址路径的第二存储器部分。在本发明的实施例中，第一数据和第一地址路径独立于第二数据和第二地址路径。响应于在第一地址路径上提供第一写地址而在第一数据路径上提供第一写入数据，同时响应于在第二地址路径上提供的读地址在第二数据路径上提供读数据。

18. 发明公开

US20230420010A1 Memory controllers, systems, and methods supporting multiple request modes 审中-公开
公开(公告)号：US20230420010A1
公开(公告)日：2023-12-28
申请号：US18340803
申请日：2023-06-23
申请人： Rambus Inc.
发明人： Richard E. Perego , Frederick A. Ware
IPC分类号： G11C7/10 , G06F13/16 , G11C5/06
CPC分类号： G11C7/1072 , G06F13/1678 , G06F13/1684 , G06F13/1694 , G11C5/06 , G11C7/1045 , G11C7/1075
摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

19. 发明授权

US11258522B2 Periodic calibration for communication channels by drift tracking 有权
公开(公告)号：US11258522B2
公开(公告)日：2022-02-22
申请号：US17024835
申请日：2020-09-18
申请人： Rambus Inc.
发明人： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
IPC分类号： H04L7/00 , H04B17/21 , H04B17/11 , H04L7/04 , H04L7/10 , H04L27/00 , H04B17/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

20. 发明授权

US11108510B2 Communication channel calibration for drift conditions 有权
公开(公告)号：US11108510B2
公开(公告)日：2021-08-31
申请号：US16861164
申请日：2020-04-28
申请人： Rambus Inc.
发明人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel
IPC分类号： H04L7/00 , H04L1/24 , H04L7/10 , H04L25/02 , H04L25/12 , G11C29/02 , G11C7/10 , H04L27/00 , G11C7/04 , H04L7/033
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

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