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11. 发明申请

US20110163780A1 Field programmable gate arrays using resistivity-sensitive memories 有权
标题翻译：使用电阻率敏感存储器的现场可编程门阵列
公开(公告)号：US20110163780A1
公开(公告)日：2011-07-07
申请号：US12932902
申请日：2011-03-08
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/1776 , H03K19/17772 , H03K19/1778
摘要： Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.
摘要翻译：描述了使用电阻率敏感存储器的现场可编程门阵列，包括包括可配置逻辑的可编程单元，连接到可配置逻辑以提供可配置逻辑的功能的存储器，存储器包括非易失性可重写存储元件，敏感存储器元件，连接到可配置逻辑的输入/输出逻辑和与其他单元通信的存储器。存储器元件可以是在没有电力的情况下存储数据的两端电阻率敏感存储器元件。两端存储器元件可以将数据存储为可以通过在存储器元件的端子上施加读取电压而被非破坏性地读取的多个导电率分布，并且可以通过施加写入电压将数据写入到两端存储器元件跨越终端。存储器可以垂直配置在一个或多个垂直堆叠在一起的并且位于逻辑平面之上的存储器平面中。

12. 发明授权

US07961529B1 Processor including vertically stacked third-dimensional embedded re-writeable non-volatile memory and registers 有权
标题翻译：处理器包括垂直堆叠的第三维嵌入式可重写非易失性存储器和寄存器
公开(公告)号：US07961529B1
公开(公告)日：2011-06-14
申请号：US12927795
申请日：2010-11-23
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C5/04 , G11C7/062 , G11C13/004 , G11C13/02 , G11C2013/0054 , G11C2013/009 , G11C2207/063 , G11C2213/13 , G11C2213/71
摘要： A non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.
摘要翻译：非易失性寄存器包括存储元件。存储元件包括第一端和第二端。非易失性寄存器包括与存储元件的第一和第二端相连的寄存器逻辑。寄存器逻辑位于存储器元件下方。存储器元件可以是被配置为将数据存储为可以通过在两个端子上施加读取电压而被非破坏性地确定的多个导电率分布的两端存储器元件。通过在两个端子上施加预定幅度和/或极性的写入电压，可以将新数据写入到两端存储元件。两端存储器元件在没有电源的情况下保留存储的数据。可以使用包括与两端存储元件相同或基本相同的结构的参考元件来产生用于在读取操作期间进行比较的参考信号。

13. 发明授权

US07961527B2 Buffering systems for accessing multiple layers of memory in integrated circuits 有权
公开(公告)号：US07961527B2
公开(公告)日：2011-06-14
申请号：US12657385
申请日：2010-01-19
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G06F13/1668 , G11C5/025 , G11C7/1012 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C2207/2218
摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

14. 发明申请

US20110062989A1 State machines using non-volatile re-writeable two-terminal resistivity-sensitive memories 失效
标题翻译：使用非易失性可重写两端电阻率敏感存储器的状态机
公开(公告)号：US20110062989A1
公开(公告)日：2011-03-17
申请号：US12927546
申请日：2010-11-15
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/173
CPC分类号： G05B19/045 , G05B2219/23289 , G11C13/00
摘要： State machines using resistivity-sensitive memory elements are disclosed. The state machine includes a next state logic comprising a non-volatile memory including a resistivity-sensitive memory element and receiving an input, a state storage device connected to the next state logic including a connection to provide a state of the state machine to the next state logic, and an output connect to the state register to output the state of the state machine. The resistivity-sensitive memory elements may be two-terminal resistivity-sensitive memory elements. The two-terminal resistivity-sensitive memory elements may store data as a plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory elements, and new data can be written by applying a write voltage across the terminals. The two-terminal resistivity-sensitive memory elements retain stored data in the absence of power and may be configured into a two-terminal cross-point memory array.
摘要翻译：公开了使用电阻率敏感记忆元件的状态机。状态机包括下一状态逻辑，其包括包括电阻率敏感存储元件和接收输入的非易失性存储器，连接到下一状态逻辑的状态存储设备，该状态存储器包括连接以将状态机的状态提供给下一个状态状态逻辑，输出连接到状态寄存器以输出状态机的状态。电阻率敏感存储元件可以是两端电阻率敏感存储元件。两端电阻率敏感存储器元件可以将数据存储为可以通过在存储器元件的端子上施加读取电压而被非破坏性读取的多个导电率分布，并且可以通过施加写入电压来写入新的数据终端。两端电阻率敏感存储器元件在没有电力的情况下保存存储的数据，并且可以被配置为两端交叉点存储器阵列。

15. 发明授权

US07903485B2 Integrated circuits and methods to compensate for defective non-volatile embedded memory in one or more layers of vertically stacked non-volatile embedded memory 有权
标题翻译：用于补偿一个或多个垂直堆叠非易失性嵌入式存储器层中的有缺陷的非易失性嵌入式存储器的集成电路和方法
公开(公告)号：US07903485B2
公开(公告)日：2011-03-08
申请号：US12807836
申请日：2010-09-14
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C29/00
CPC分类号： G11C5/02 , G11C29/808
摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third dimension memory technology. In a specific embodiment, an integrated circuit is configured to compensate for defective memory cells. For example, the integrated circuit can include a memory having memory cells that are disposed in multiple layers of memory. It can also include a memory reclamation circuit configured to substitute a subset of the memory cells for one or more defective memory cells. At least one memory cell in the subset of the memory cells resides in a different plane in the memory than at least one of the one or more defective memory cells.
摘要翻译：本发明的实施例一般涉及数据存储和计算机存储器，更具体地涉及用于补偿第三维存储器技术中的有缺陷的存储器的系统，集成电路和方法。在具体实施例中，集成电路被配置为补偿有缺陷的存储器单元。例如，集成电路可以包括具有设置在多层存储器中的存储器单元的存储器。它还可以包括配置为将存储器单元的子集替换为一个或多个有缺陷的存储器单元的存储器回收电路。存储器单元的子集中的至少一个存储单元驻留在存储器中的不同于所述一个或多个缺陷存储器单元中的至少一个的不同平面中。

16. 发明授权

US07839702B2 Three-dimensional non-volatile register with an oxygen-ion-based memory element and a vertically-stacked register logic 有权
标题翻译：具有基于氧离子的存储元件和垂直堆叠的寄存器逻辑的三维非易失性寄存器
公开(公告)号：US07839702B2
公开(公告)日：2010-11-23
申请号：US12800289
申请日：2010-05-11
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C5/04 , G11C7/062 , G11C13/004 , G11C13/02 , G11C2013/0054 , G11C2013/009 , G11C2207/063 , G11C2213/13 , G11C2213/71
摘要： A non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.
摘要翻译：非易失性寄存器包括存储元件。存储元件包括第一端和第二端。非易失性寄存器包括与存储元件的第一和第二端相连的寄存器逻辑。寄存器逻辑位于存储器元件下方。存储器元件可以是被配置为将数据存储为可以通过在两个端子上施加读取电压而被非破坏性地确定的多个导电率分布的两端存储器元件。通过在两个端子上施加预定幅度和/或极性的写入电压，可以将新数据写入到两端存储元件。两端存储器元件在没有电源的情况下保留存储的数据。可以使用包括与两端存储元件相同或基本相同的结构的参考元件来产生用于在读取操作期间进行比较的参考信号。

17. 发明申请

US20100293355A1 Fast data access through page manipulation 有权
公开(公告)号：US20100293355A1
公开(公告)日：2010-11-18
申请号：US12804630
申请日：2010-07-26
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F12/00
CPC分类号： G11C5/066 , G11C7/1051 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C2207/107 , G11C2216/30
摘要： A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and, when the page buffer module is full with aligned data, transferring the aligned data to the memory. The method includes receiving data at an interface, aligning the data to generate aligned data, storing aligned data in a page buffer module configured to store aligned data for a write access and retrieved data from a read access, writing aligned data to a memory, and transferring retrieved data to the interface. Data can be transferred by the interface at a first rate and aligned data can be written to or retrieved from the memory at substantially the first rate.

18. 发明申请

US20100195362A1 Non-volatile dual port third dimensional memory 有权
标题翻译：非易失性双端口三维存储器
公开(公告)号：US20100195362A1
公开(公告)日：2010-08-05
申请号：US12592319
申请日：2009-11-23
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C5/02 , G11C11/00 , G11C7/00
CPC分类号： G11C7/1075 , G11C8/14 , G11C8/16
摘要： Non-volatile dual port memory with third dimension memory is described, including a non-volatile third dimensional memory array comprising a memory element, the memory element is configured to change from a first resistive state to a second resistive state in response to a voltage, a transceiver gate configured to gate the voltage to the memory element, the voltage being configured to change the memory element from the first resistive state to the second resistive state, the transceiver gate is configured to receive another voltage from a bit line and a bit bar line, the bit line and the bit bar line being coupled to the memory element and configured to provide the another voltage, and a plurality of word lines coupled to the memory element, the plurality of word lines are configured to provide substantially simultaneous access to the non-volatile third dimensional memory array using two or more ports.
摘要翻译：描述了具有第三维存储器的非易失性双端口存储器，包括包括存储器元件的非易失性第三维存储器阵列，该存储器元件被配置为响应于电压从第一电阻状态改变到第二电阻状态，收发器门被配置为将电压栅极存储到存储器元件，该电压被配置为将存储元件从第一电阻状态改变到第二电阻状态，收发器门被配置为从位线和位条接收另一电压线，位线和位线连接到存储器元件并且被配置为提供另一电压，以及耦合到存储器元件的多个字线，多个字线被配置为提供基本上同时的访问使用两个或多个端口的非易失性第三维存储器阵列。

19. 发明申请

US20100162065A1 Protecting integrity of data in multi-layered memory with data redundancy 审中-公开
标题翻译：通过数据冗余保护多层内存中数据的完整性
公开(公告)号：US20100162065A1
公开(公告)日：2010-06-24
申请号：US12586416
申请日：2009-09-21
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F11/20 , G06F11/00
CPC分类号： H03M7/30 , G11C5/02
摘要： Systems, integrated circuits, and methods for protecting data stored in third dimensional vertically stacked memory technology are disclosed. An integrated circuit is configured to perform duplication of data disposed in multi-layered memory that can comprise two-terminal cross-point memory arrays fabricated BEOL on top of a FEOL logic layer that includes active circuitry for performing data operations (e.g., read, write, program, and erase) on the multi-layered memory. For example, the integrated circuit can include a first subset of BEOL memory layers configured to store data, a second subset of the BEOL memory layers configured to store a copy of the data from the first subset of memory layers, a FEOL redundancy circuit coupled to the first subset of the memory layers and the second subset of the memory layers, the redundancy circuit being configured to provide both a portion of the data and a copy of the portion of the data.
摘要翻译：公开了用于保护存储在第三维垂直堆叠存储器技术中的数据的系统，集成电路和方法。集成电路被配置为执行设置在多层存储器中的数据的复制，其可以包括在包括用于执行数据操作的有源电路（例如，读取，写入）的FEOL逻辑层之上制造的BEOL的两端交叉点存储器阵列，程序和擦除）在多层内存上。例如，集成电路可以包括被配置为存储数据的BEOL存储器层的第一子集，BEOL存储器层的第二子集被配置为存储来自存储器层的第一子集的数据的副本，耦合到存储器层的第一子集和存储器层的第二子集，冗余电路被配置为提供数据的一部分和数据的该部分的副本。

20. 发明申请

US20100157644A1 Configurable memory interface to provide serial and parallel access to memories 审中-公开
标题翻译：可配置的存储器接口提供串行和并行访问存储器
公开(公告)号：US20100157644A1
公开(公告)日：2010-06-24
申请号：US12587841
申请日：2009-10-13
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C5/02 , G11C7/00 , G11C5/06
CPC分类号： G11C7/1045 , G11C5/00 , G11C7/10 , G11C8/10
摘要： The invention relates to an interface for providing multiple modes of accessing data, including serial and parallel modes. Controllable non-volatile memory interfaces are described, including a serial module configured to provide a serial connection between a non-volatile memory array and another non-volatile memory array. The serial module can provide access to the non-volatile memory array. A mode module can be configured to determine which type of interface operation (i.e., serial mode or parallel mode) will be used for the non-volatile memory array and the another non-volatile memory array. In some cases, a controller can be configured to select the serial module independent of the mode module. Circuitry for performing data operations on the non-volatile memories can be fabricated FEOL on a substrate and the non-volatile memories can be fabricated BEOL directly on top of the substrate in one or more layers of memory.
摘要翻译：本发明涉及一种用于提供多种访问数据模式的接口，包括串行和并行模式。描述了可控非易失性存储器接口，包括被配置为提供非易失性存储器阵列与另一非易失性存储器阵列之间的串行连接的串行模块。串行模块可以提供对非易失性存储器阵列的访问。可以将模式模块配置为确定将用于非易失性存储器阵列和另一非易失性存储器阵列的哪种类型的接口操作（即串行模式或并行模式）。在某些情况下，控制器可以配置为独立于模式模块选择串行模块。用于对非易失性存储器执行数据操作的电路可以在衬底上制造为FEOL，并且非易失性存储器可以在一个或多个存储器层中直接在衬底的顶部上制造BEOL。

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