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11. 发明授权

US11423975B2 Memory device and method of operating the same 有权
公开(公告)号：US11423975B2
公开(公告)日：2022-08-23
申请号：US16968922
申请日：2019-02-13
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Yuki Okamoto , Tatsuya Onuki
IPC分类号： G11C11/4097 , G11C11/4091 , H01L27/105 , H01L27/12 , H01L29/24 , H01L29/786
摘要： A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are provided to overlap with each other. Two bit lines included in the first bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. Two bit lines included in the second bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. In the first cell array, one of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair. In the second cell array, the other of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair.

12. 发明授权

US11366507B2 Storage device, semiconductor device, electronic component, and electronic device 有权
公开(公告)号：US11366507B2
公开(公告)日：2022-06-21
申请号：US17104460
申请日：2020-11-25
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shuhei Maeda , Shuhei Nagatsuka , Tatsuya Onuki , Kiyoshi Kato
IPC分类号： G11C14/00 , G06F1/3234 , G11C5/14 , G11C16/30
摘要： To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

13. 发明授权

US11289475B2 Semiconductor device and manufacturing method of semiconductor device 有权
公开(公告)号：US11289475B2
公开(公告)日：2022-03-29
申请号：US16695385
申请日：2019-11-26
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Shunpei Yamazaki , Tatsuya Onuki , Katsuaki Tochibayashi
IPC分类号： H01L29/786 , H01L27/06 , H01L29/45
摘要： A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a transistor and a capacitor. The transistor includes a first conductor and a second insulator over a first insulator; a third insulator over the first conductor and the second insulator; a fourth insulator over the third insulator; a first oxide over the fourth insulator; a second oxide and a third oxide over the first oxide; a second conductor in contact with a top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the second oxide, and a top surface of the second oxide; a third conductor in contact with the top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the third oxide, and a top surface of the third oxide; a fourth oxide over the first oxide; a fifth insulator over the fourth oxide; and a fourth conductor over the fifth insulator. The capacitor includes a fifth conductor over the first insulator, the third insulator over the fifth conductor, and the second conductor over the third insulator.

14. 发明授权

US11270997B2 Memory device 有权
公开(公告)号：US11270997B2
公开(公告)日：2022-03-08
申请号：US16757025
申请日：2018-11-19
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Tatsuya Onuki , Yuki Okamoto , Hisao Ikeda , Shuhei Nagatsuka
IPC分类号： H01L27/00 , H01L29/00 , H01L27/105 , H01L27/12 , H01L29/786
摘要： A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are stacked. One of two bit lines of a first bit line pair is electrically connected to A memory cells of the first cell array, and the other of the two bit lines of the first bit line pair is electrically connected to D memory cells of the second cell array. One of two bit lines of a second bit line pair is electrically connected to B memory cells of the first cell array and F memory cells of the second cell array, and the other of the two bit lines of the second bit line pair is electrically connected to C memory cells of the first cell array and E memory cells of the second cell array. The first bit line pairs and the second bit line pairs are alternately provided.

15. 发明授权

US11056491B2 Semiconductor device and method for manufacturing semiconductor device 有权
公开(公告)号：US11056491B2
公开(公告)日：2021-07-06
申请号：US16623648
申请日：2018-06-19
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei Yamazaki , Daisuke Matsubayashi , Tatsuya Onuki
IPC分类号： H01L27/105 , H01L27/12 , H01L29/786 , H01L21/02 , H01L21/4757 , H01L29/24 , H01L29/66 , H01L21/477
摘要： A semiconductor device that can be highly integrated is provided. The semiconductor device includes a transistor, an interlayer film, and a first conductor. The transistor includes an oxide over a first insulator; a second conductor over the oxide; a second insulator provided between the oxide and the second conductor and in contact with a side surface of the second conductor; and a third insulator provided for the side surface of the second conductor with the second insulator therebetween. The oxide includes a first region, a second region, and a third region. The first region overlaps with the second conductor. The second region is provided between the first region and the third region. The third region has a lower resistance than the second region. The second region has a lower resistance than the first region. The interlayer film is provided over the first insulator and the oxide. The first conductor is electrically connected to the third region. The third region overlaps with one of the third insulator, the first conductor, and the interlayer film. A top surface of the third insulator is level with a top surface of the interlayer film.

16. 发明授权

US10170175B2 Semiconductor device comprising memory devices each comprising sense amplifier and memory cell 有权
公开(公告)号：US10170175B2
公开(公告)日：2019-01-01
申请号：US14705698
申请日：2015-05-06
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Kiyoshi Kato , Tatsuya Onuki
IPC分类号： G11C11/4096 , G11C11/4091 , G11C11/4097
摘要： A memory device with low power consumption is provided. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer comprising the sense amplifier. The memory cells are provided over a layer comprising the bit lines. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor.

17. 发明授权

US09704562B2 Semiconductor device with stacked structure of memory cells over sensing amplifiers, circuit board, and electronic device 有权
公开(公告)号：US09704562B2
公开(公告)日：2017-07-11
申请号：US14872535
申请日：2015-10-01
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tatsuya Onuki , Kiyoshi Kato , Wataru Uesugi , Takahiko Ishizu
IPC分类号： G11C7/00 , G11C11/4091 , G11C7/02 , G11C11/4094 , G11C11/4097 , H01L27/108 , G11C5/02
CPC分类号： G11C11/4091 , G11C5/025 , G11C7/02 , G11C11/4094 , G11C11/4097 , G11C2213/71 , H01L27/10808
摘要： A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.

18. 发明授权

US09640255B2 Semiconductor device and driving method of semiconductor device 有权
公开(公告)号：US09640255B2
公开(公告)日：2017-05-02
申请号：US15081998
申请日：2016-03-28
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tatsuya Onuki , Wataru Uesugi
IPC分类号： G11C5/06 , G11C14/00 , G11C5/10
CPC分类号： G11C14/0054 , G11C5/063 , G11C5/10
摘要： To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.

19. 发明授权

US09391598B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09391598B2
公开(公告)日：2016-07-12
申请号：US15001338
申请日：2016-01-20
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hiroki Inoue , Kei Takahashi , Tatsuya Onuki
IPC分类号： H03L5/00 , H03K5/24
CPC分类号： H03K5/2481 , G11C27/024 , G11C27/026 , H03K5/249
摘要： A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation. Then, it holds the potential of the capacitor through holding operation. In normal operation of the differential circuit, the output potential of the differential circuit is corrected by the potential held by the capacitor. The transistor in the sample-and-hold circuit is preferably a transistor whose channel is formed using an oxide semiconductor. An oxide semiconductor transistor has extremely low leakage current; thus, a change in the potential held in the capacitor of the sample-and-hold circuit can be minimized.
摘要翻译：包括晶体管和电容器的采样保持电路连接到差分电路。采样保持电路通过采样操作对电容器进行充电或放电来获取用于校正差分电路的偏移电压的电压。然后，它通过保持操作保持电容器的电位。在差分电路的正常工作中，差分电路的输出电位由电容器保持的电位进行校正。采样保持电路中的晶体管优选地是使用氧化物半导体形成沟道的晶体管。氧化物半导体晶体管具有极低的漏电流; 因此，可以使采样保持电路的电容器中保持的电位变化最小化。

20. 发明申请

US20150109870A1 ARITHMETIC PROCESSING UNIT AND DRIVING METHOD THEREOF 有权
标题翻译：算术处理单元及其驱动方法
公开(公告)号：US20150109870A1
公开(公告)日：2015-04-23
申请号：US14515949
申请日：2014-10-16
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Takahiko Ishizu , Kiyoshi Kato , Tatsuya Onuki
IPC分类号： G11C5/14 , G11C7/22
CPC分类号： G11C11/419 , G11C11/412
摘要： An arithmetic processing unit including an SRAM with low power consumption and performing backup and recovery operation with no burden on circuits. One embodiment is a memory device including a plurality of memory cells. The memory cells include inverters in which capacitors for backing up data are provided. When data of all the memory cells in a region is not rewritten after data is returned from the capacitors to the inverters, data in the region is not transferred from the inverters to the capacitors and the inverters are turned off. When data of at least one of the memory cells in the region is rewritten, data in the region is transferred from the inverters to the capacitors and then power of the inverters are turned off. In this manner, backup is selectively performed to reduce power consumption. Other embodiments are described and claimed.
摘要翻译：一种算术处理单元，包括具有低功耗的SRAM，并执行备份和恢复操作，而不会对电路造成负担。一个实施例是包括多个存储单元的存储器件。存储单元包括其中提供用于备份数据的电容器的反相器。在数据从电容器返回到逆变器之后，当区域中的所有存储单元的数据不被重写时，该区域中的数据不会从反相器传送到电容器，并且反相器被关断。当该区域中的至少一个存储单元的数据被重写时，该区域中的数据从反相器传送到电容器，然后逆变器的电源被关断。以这种方式，选择性地执行备份以降低功耗。描述和要求保护其他实施例。

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