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11. 发明授权

US09501602B2 Electromigration-aware layout generation 有权
标题翻译：电迁移感知布局生成
公开(公告)号：US09501602B2
公开(公告)日：2016-11-22
申请号：US14255325
申请日：2014-04-17
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Nitesh Katta , Jerry Chang-Jui Kao , Chin-Shen Lin , Yi-Chuin Tsai , Chou-Kun Lin , Kuo-Nan Yang , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036 , G06F2217/78 , G06F2217/82 , G06F2217/84
摘要： In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment.
摘要翻译：在一些实施例中，在一种方法中，执行设计布局的放置。设计布局包括电力轨道段，几个上级电力线和几个电池。上层电力线在电力轨道段上交叉并限制在上层电力线与电力轨道段相交的位置。电池通过电源轨段供电。对于每个电池，获得在电池的相应SW期间通过电力轨道段的相应电流。确定具有重叠SW的一组或多组细胞。获得使用每组单元的各自电流的一组或多组单元的电力轨道段的一个或多个EM用途。当电力轨道段的一个或多个EM使用中的任何一个导致电力轨道段的EM敏感性时，调整设计布局。

12. 发明授权

US09471738B2 Method and apparatus for capacitance extraction 有权
标题翻译：电容提取方法和装置
公开(公告)号：US09471738B2
公开(公告)日：2016-10-18
申请号：US14615084
申请日：2015-02-05
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chih-Cheng Chou , Tsung-Han Wu , Ke-ying Su , Hsien-Hsin Sean Lee , Chung-Hsing Wang
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5081
摘要： A method comprises processing a layout of an integrated circuit to determine one or more attributes of one or more components of the integrated circuit. The method also comprises extracting one or more process parameters from a process file associated with manufacturing the integrated circuit. The one or more process parameters are extracted from the process file based on a computation of one or more logic functions included in the process file. The computation is based on the one or more attributes. The method further comprises calculating a capacitance value between at least two components of the integrated circuit based on the one or more process parameters and a capacitance determination rule included in the process file. At least one of the one or more process parameters, the one or more logic functions, or the capacitance determination rule is editable based on a user input.
摘要翻译：一种方法包括处理集成电路的布局以确定集成电路的一个或多个组件的一个或多个属性。该方法还包括从与制造集成电路相关联的处理文件中提取一个或多个处理参数。基于包括在处理文件中的一个或多个逻辑功能的计算，从处理文件中提取一个或多个处理参数。计算基于一个或多个属性。该方法还包括基于一个或多个处理参数和包括在处理文件中的电容确定规则来计算集成电路的至少两个分量之间的电容值。一个或多个处理参数，一个或多个逻辑功能或电容确定规则中的至少一个可以基于用户输入进行编辑。

13. 发明授权

US09367660B2 Electromigration-aware layout generation 有权
标题翻译：电迁移感知布局生成
公开(公告)号：US09367660B2
公开(公告)日：2016-06-14
申请号：US14218147
申请日：2014-03-18
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Nitesh Katta , Jerry Chang-Jui Kao , Chin-Shen Lin , Yi-Chuin Tsai , Chien-Ju Chao , Kuo-Nan Yang , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5068 , G06F17/5072 , G06F17/5077
摘要： In some embodiments, in a method, cell layouts of a plurality of cells are received. For each cell, a respective constraint that affects a geometry of an interconnect to be coupled to an output pin of the cell in a design layout is determined based on a geometry of the output pin of the cell in the cell layout.
摘要翻译：在一些实施例中，在一种方法中，接收多个单元的单元布局。对于每个单元，基于单元格布局中的单元的输出引脚的几何形状来确定影响要在设计布局中耦合到单元的输出引脚的互连的几何形状的相应约束。

14. 发明申请

US20160162619A1 Cell Having Shifted Boundary and Boundary-Shift Scheme 审中-公开
标题翻译：移位边界和边界移位方案
公开(公告)号：US20160162619A1
公开(公告)日：2016-06-09
申请号：US15043858
申请日：2016-02-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Nan Yang , Chou-Kun Lin , Jerry Chang-Jui Kao , Yi-Chuin Tsai , Chien-Ju Chao , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5081
摘要： An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.
摘要翻译：实施例小区移位方案包括将第一晶体管单元抵靠第二晶体管单元并将位置和布线边界移离设置在第一晶体管单元和第二晶体管单元之间的多晶硅。在一个实施例中，小区移位方案包括移动位置和路由边界以防止布局与示意图（LVS）网表和后仿真网表之间的不匹配。

15. 发明授权

US09287257B2 Power gating for three dimensional integrated circuits (3DIC) 有权
标题翻译：三维集成电路的电源门控（3DIC）
公开(公告)号：US09287257B2
公开(公告)日：2016-03-15
申请号：US14470716
申请日：2014-08-27
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chien-Ju Chao , Chou-Kun Lin , Yi-Chuin Tsai , Yen-Hung Lin , Po-Hsiang Huang , Kuo-Nan Yang , Chung-Hsing Wang
IPC分类号： H01L27/06 , H01L27/02 , H01L23/528 , H01L23/50 , H01L21/768 , H01L21/324 , H01L21/8234
CPC分类号： H01L27/0207 , H01L21/324 , H01L21/768 , H01L21/8221 , H01L21/823475 , H01L21/823871 , H01L23/50 , H01L23/528 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L23/5329 , H01L27/0203 , H01L27/0688 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.
摘要翻译：在本公开中描述了在多个有源器件层上形成功率门控单元和虚拟功率电路的机构的实施例。电源门控单元和虚拟电源电路形成在单独的有源器件层上，以允许与电源连接的互连结构形成在与用于连接电源门控单元和虚拟电源电路的互连结构的单独级别上。这种分离防止这两种类型的互连结构竞争相同的空间。两种类型的互连结构的路由变得更加容易。结果，互连结构的金属长度减小并且金属宽度增加。减少金属长度和增加的金属宽度降低电阻，提高电阻 - 电容（RC）延迟和电气性能，并提高互连可靠性，如减少电迁移。

16. 发明授权

US09223922B2 Semiconductor device design method 有权
标题翻译：半导体器件设计方法
公开(公告)号：US09223922B2
公开(公告)日：2015-12-29
申请号：US14658749
申请日：2015-03-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ping-Hung Yuh , Cheng-I Huang , Chung-Hsing Wang
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/5081
摘要： A method of generating a netlist comprises extracting a first capacitance value between the first set of electrical components inside a defined region using a first extraction technique. The method additionally comprises extracting a second capacitance value between a second set of electrical components comprising at least one electrical component outside the defined region using a second extraction technique different from the first extraction technique. The method also comprises generating the netlist including the first capacitance value and the second capacitance value. The first extraction technique is capable of extracting capacitance values between electrical components arranged in a first quantity of directions with respect to one another and the second extraction technique is capable of extracting capacitance values between electrical components arranged in a second quantity of directions with respect to one another. The first quantity of directions is greater than the second quantity of directions.
摘要翻译：生成网表的方法包括使用第一提取技术在限定区域内的第一组电组件之间提取第一电容值。该方法还包括使用不同于第一提取技术的第二提取技术，在包括限定区域外的至少一个电气部件的第二组电气部件之间提取第二电容值。该方法还包括生成包括第一电容值和第二电容值的网表。第一提取技术能够提取在相对于彼此的第一数量方向布置的电气部件之间的电容值，并且第二提取技术能够提取相对于一个方向布置在第二数量方向上的电气部件之间的电容值另一个。第一数量的方向大于第二数量的方向。

17. 发明授权

US09129956B2 Device having multiple-layer pins in memory MUX1 layout 有权
标题翻译：在存储器MUX1布局中具有多层引脚的器件
公开(公告)号：US09129956B2
公开(公告)日：2015-09-08
申请号：US14102623
申请日：2013-12-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Hung-Jen Liao , Jung-Hsuan Chen , Chien Chi Tien , Ching-Wei Wu , Jui-Che Tsai , Hong-Chen Cheng , Chung-Hsing Wang
IPC分类号： H01L23/00 , H01L23/498 , H01L27/11 , H01L23/532 , H01L27/02 , H01L23/528
CPC分类号： H01L23/50 , H01L23/49811 , H01L23/49827 , H01L23/5226 , H01L23/528 , H01L23/53204 , H01L27/0203 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) memory device that includes a first conductive layer, a second conductive layer electrically coupled to the first conductive layer, the second conductive layer formed over the first conductive layer, a third conductive layer separated from the second conductive layer, the third conductive layer formed over the second conductive layer, a fourth conductive layer electrically coupled to the third conductive layer, the fourth conductive layer formed over the third conductive layer, a 2P2E pin box formed in and electrically coupled to the first conductive layer or the second conductive layer and a 1P1E pin box formed in and electrically coupled to the third conductive layer or the fourth conductive layer.
摘要翻译：一种集成电路（IC）存储器件，其包括第一导电层，电耦合到第一导电层的第二导电层，形成在第一导电层上的第二导电层，与第二导电层分离的第三导电层，形成在所述第二导电层上的第三导电层，电耦合到所述第三导电层的第四导电层，形成在所述第三导电层上的所述第四导电层，形成在所述第一导电层中或与所述第二导电层电连接的第二导电层，导电层和形成在第三导电层或第四导电层中并电耦合到第三导电层的1P1E引脚盒。

18. 发明授权

US09111065B2 Method for dummy metal and dummy via insertion 有权
标题翻译：虚拟金属和虚拟通孔插入方法
公开(公告)号：US09111065B2
公开(公告)日：2015-08-18
申请号：US14156590
申请日：2014-01-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Hung-Yi Liu , Chung-Hsing Wang , Chih-Chieh Chen , Jian-Yi Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5045 , G06F17/5068 , G06F17/5072 , G06F17/5081
摘要： A method of inserting dummy metal and dummy via in an integrated circuit design includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design, and the dummy metals have a length less than or equal to a predetermined maximum length. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals.
摘要翻译：在集成电路设计中插入虚拟金属和虚拟通孔的方法包括通过计算机使用放置和布线工具插入虚拟金属，其中放置和布线工具具有时间意识以提高集成电路设计的定时性能并且所述虚拟金属具有小于或等于预定最大长度的长度。该方法还包括使用与插入虚拟金属分离的设计规则检查实用程序，由计算机插入虚拟通孔。

19. 发明授权

US08847284B2 Integrated circuit with standard cells 有权
标题翻译：集成电路与标准单元
公开(公告)号：US08847284B2
公开(公告)日：2014-09-30
申请号：US13829484
申请日：2013-03-14
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Nan Yang , Chou-Kun Lin , Jerry Chang-Jui Kao , Yi-Chuin Tsai , Chien-Ju Chao , Chung-Hsing Wang
IPC分类号： H01L27/10 , H01L27/02
CPC分类号： H01L27/0207 , H01L27/11807
摘要： A die includes a plurality of rows of standard cells. Each of all standard cells in the plurality of rows of standard cells includes a transistor and a source edge, wherein a source region of the transistor is adjacent to the source edge. No drain region of any transistor in the each of all standard cells is adjacent to the source region.
摘要翻译：芯片包括多行标准单元。多行标准单元中的每个标准单元包括晶体管和源极边缘，其中晶体管的源极区域与源极边缘相邻。所有标准单元中的每一个中的任何晶体管的漏极区域都不与源极区域相邻。

20. 发明申请

US20140245251A1 Design Optimization for Circuit Migration 审中-公开
标题翻译：电路迁移的设计优化
公开(公告)号：US20140245251A1
公开(公告)日：2014-08-28
申请号：US14268845
申请日：2014-05-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5068 , G06F17/5072
摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.
摘要翻译：本发明的实施例是一种用于提供集成电路布局的经调整的电子表示的计算机程序产品。计算机程序产品具有其上体现计算机程序的介质。此外，计算机程序包括用于从完整节点网表提供全节点单元的计算机程序代码，用于缩放全节点单元以提供收缩节点单元的计算机程序代码，用于提供全节点单元的定时性能的计算机程序代码和收缩节点单元，用于将全节点单元的定时性能与收缩节点单元的定时性能进行比较的计算机程序代码以及用于提供第一网表的计算机程序代码。

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