专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07663907B2 Die customization using programmable resistance memory elements 有权
标题翻译：使用可编程电阻存储元件进行模具定制
公开(公告)号：US07663907B2
公开(公告)日：2010-02-16
申请号：US11229955
申请日：2005-09-19
申请人： Tyler Lowrey , Guy C. Wicker , Edward J. Spall
发明人： Tyler Lowrey , Guy C. Wicker , Edward J. Spall
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2013/0083 , G11C2029/4402
摘要： A method of customizing an integrated circuit chip, comprising the steps of: providing an electronic circuit on said chip; providing a phase-change memory on the chip; storing information about said electronic circuit in the phase-change memory. A method of operating an optical display.
摘要翻译：一种定制集成电路芯片的方法，包括以下步骤：在所述芯片上提供电子电路; 在芯片上提供相变存储器; 将关于所述电子电路的信息存储在相变存储器中。一种操作光学显示器的方法。

12. 发明申请

US20090034325A1 Programmable matrix array with chalcogenide material 有权
标题翻译：具有硫属化物材料的可编程矩阵阵列
公开(公告)号：US20090034325A1
公开(公告)日：2009-02-05
申请号：US12286784
申请日：2008-10-02
申请人： Tyler Lowrey , Ward Parkinson , Guy Wicker
发明人： Tyler Lowrey , Ward Parkinson , Guy Wicker
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/72 , G11C2213/75 , G11C2213/76 , G11C2213/79 , H01L27/2427
摘要： A chalcogenide material is proposed for programming the cross-connect transistor coupling interconnect lines of an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer in series with the select device or a phase change material. The matrix array may be used in a programmable logic device.
摘要翻译：提出硫族化物材料来编程电可编程矩阵阵列的交叉连接晶体管耦合互连线。可以通过选择性地将薄绝缘击穿层与选择装置或相变材料串联来减小泄漏。矩阵阵列可以用在可编程逻辑器件中。

13. 发明申请

US20090029031A1 Methods for forming electrodes in phase change memory devices 审中-公开
标题翻译：在相变存储器件中形成电极的方法
公开(公告)号：US20090029031A1
公开(公告)日：2009-01-29
申请号：US12113566
申请日：2008-05-01
申请人： Tyler Lowrey
发明人： Tyler Lowrey
IPC分类号： B05D5/12
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A method for forming electrode materials uniformly within openings having small dimensions, including sublithographic dimensions, or high aspect ratios. The method includes the steps of providing an insulator layer having an opening formed therein, forming a non-conformal conductive or semiresistive material over and within the opening, and mobilizing the conductive material to densify it within the opening. The method reduces the concentration of voids or defects in the conductive or semiresistive material relative to the as-deposited state. The mobilizing step may be accomplished by extrusion or thermal reflow and causes voids or defects to coalesce, collapse, percolate, or otherwise be removed from the as-deposited conductive or semiresistive material.
摘要翻译：一种用于在具有小尺寸的开口内均匀地形成电极材料的方法，包括亚光刻尺寸或高纵横比。该方法包括提供具有形成在其中的开口的绝缘体层的步骤，在开口内部和内部形成非共形导电或半永久材料，并且动员导电材料以在开口内使其致密化。该方法相对于沉积状态降低导电或半主体材料中的空隙或缺陷的浓度。移动步骤可以通过挤出或热回流来实现，并且导致空隙或缺陷聚结，塌陷，渗滤或以其它方式从沉积的导电或半主体材料中除去。

14. 发明申请

US20080273372A1 Method of Programming Multi-Layer Chalcogenide Devices 有权
标题翻译：多层硫族化物器件编程方法
公开(公告)号：US20080273372A1
公开(公告)日：2008-11-06
申请号：US12178148
申请日：2008-07-23
申请人： Regino Sandoval , Sergey A. Kostylev , Wolodymyr Czubatyj , Tyler Lowrey
发明人： Regino Sandoval , Sergey A. Kostylev , Wolodymyr Czubatyj , Tyler Lowrey
IPC分类号： G11C11/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625
摘要： A method of programming a multi-layer chalcogenide electronic device. The device includes an active region in electrical communication with two terminals, where the active region includes two or more layers. The method includes providing an electrical signal between the two terminals, where the electrical signal alters an electrical characteristic of a layer remote from one of the terminals. In one embodiment, the layer remote from the terminal is a chalcogenide material and the electrical characteristic is resistance. In another embodiment, an electrical characteristic of the layer in contact with the terminal is also altered. The alteration of an electrical characteristic may be caused by a transformation of a chalcogenide material from one structural state to another structural state.
摘要翻译：一种编程多层硫族化物电子器件的方法。该器件包括与两个端子电连通的有源区域，其中有源区域包括两层或更多层。该方法包括在两个终端之间提供电信号，其中电信号改变远离一个终端的层的电特性。在一个实施例中，远离终端的层是硫族化物材料，并且电特性是电阻。在另一个实施例中，与终端接触的层的电特性也被改变。电特性的改变可能是由硫族化物材料从一种结构状态转变为另一种结构状态引起的。

15. 发明申请

US20080272807A1 Thin film logic device and system 有权
标题翻译：薄膜逻辑器件和系统
公开(公告)号：US20080272807A1
公开(公告)日：2008-11-06
申请号：US12157049
申请日：2008-06-06
申请人： Tyler Lowrey
发明人： Tyler Lowrey
IPC分类号： H03K19/00 , G11C11/00 , H01L29/06
CPC分类号： H03K19/1733
摘要： Thin film logic circuits employ thin-film switching devices to execute complementary logic functions. Such logic devices operate, as complementary metal oxide semiconductor (CMOS) logic devices do, in a manner that does not provide a direct conduction path between a system supply and a system return. Complementary logic circuits may employ three-terminal threshold switches as switching elements.
摘要翻译：薄膜逻辑电路采用薄膜开关器件来执行互补的逻辑功能。作为互补金属氧化物半导体（CMOS）逻辑器件，这样的逻辑器件以不提供系统电源和系统返回之间的直接传导路径的方式工作。互补逻辑电路可以采用三端口阈值开关作为开关元件。

16. 发明申请

US20080224734A1 Multi-terminal chalcogenide logic circuits 有权
标题翻译：多端硫族化物逻辑电路
公开(公告)号：US20080224734A1
公开(公告)日：2008-09-18
申请号：US11724485
申请日：2007-03-15
申请人： Tyler Lowrey
发明人： Tyler Lowrey
IPC分类号： H03K19/00 , H01L45/00
CPC分类号： H03K19/1733
摘要： Logic circuits are disclosed that include one or more three-terminal chalcogenide devices. The three-terminal chalcogenide devices are electrically interconnected and configured to perform one or more logic operations, including AND, OR, NOT, NAND, NOR, XOR, and XNOR. Embodiments include series and parallel configurations of three-terminal chalcogenide devices. The chalcogenide devices include a chalcogenide switching material as the working medium along with three electrical terminals in electrical communication therewith.In one embodiment, the circuits include one or more input terminals, one or more output terminals, and a clock terminal. The input terminals receive one or more input signals and deliver them to the circuit for processing according to a logic operation. Upon conclusion of processing, the output of the circuit is provided to the output terminal. The clock terminal delivers a clock signal to facilitate operation of the three-terminal devices included in the instant circuits. In one embodiment, the clock signal includes an ON cycle and an OFF cycle, where the circuit performs a logic operation during the ON cycle and any three-terminal devices that are switched to the conductive state during the ON cycle are returned to their resistive state during the OFF cycle.
摘要翻译：公开了包括一个或多个三末端硫族化物装置的逻辑电路。三端硫属化物器件电互连并被配置为执行一个或多个逻辑操作，包括AND，OR，NOT，NAND，NOR，XOR和XNOR。实施方案包括三末端硫族化物装置的串联和并联配置。硫族化物装置包括作为工作介质的硫族化物转换材料以及与其电连通的三个电端子。在一个实施例中，电路包括一个或多个输入端子，一个或多个输出端子和时钟端子。输入端子接收一个或多个输入信号，并根据逻辑运算将它们传送到电路进行处理。在处理结束时，将电路的输出提供给输出端。时钟终端提供时钟信号，以便于即时电路中包括的三端设备的操作。在一个实施例中，时钟信号包括ON周期和OFF周期，其中电路在ON周期期间执行逻辑运算，并且在ON周期期间切换到导通状态的任何三端器件返回到其电阻状态在OFF循环期间。

17. 发明申请

US20080224120A1 Phase change device with offset contact 有权
标题翻译：相移装置，带偏置接点
公开(公告)号：US20080224120A1
公开(公告)日：2008-09-18
申请号：US12152330
申请日：2008-05-14
申请人： Wolodymyr Czubatyj , Tyler Lowrey
发明人： Wolodymyr Czubatyj , Tyler Lowrey
IPC分类号： H01L45/00
CPC分类号： H01L45/126 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/141
摘要： A programmable resistance memory combines multiple cells into a block that includes one or more shared electrodes. The shared electrode configuration provides additional thermal isolation for the active region of each memory cell, thereby reducing the current required to program each memory cell.
摘要翻译：可编程电阻存储器将多个单元组合成包括一个或多个共享电极的块。共享电极配置为每个存储单元的有源区域提供额外的热隔离，从而减少编程每个存储单元所需的电流。

18. 发明申请

US20080067492A1 Three-dimensional phase-change memory 有权
公开(公告)号：US20080067492A1
公开(公告)日：2008-03-20
申请号：US11522584
申请日：2006-09-18
申请人： Tyler Lowrey
发明人： Tyler Lowrey
IPC分类号： H01L29/06
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements disposed above the first and second plurality of diodes and a second plurality of memory elements disposed above the first plurality of memory elements.

19. 发明申请

US20080067491A1 Phase change material memory device 审中-公开
公开(公告)号：US20080067491A1
公开(公告)日：2008-03-20
申请号：US11986145
申请日：2007-11-20
申请人： Tyler Lowrey
发明人： Tyler Lowrey
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L45/124 , H01L45/1253 , H01L45/1293 , H01L45/144 , H01L45/1691
摘要： A lower electrode may be covered by a protective film to reduce the exposure of the lower electrode to subsequent processing steps or the open environment. As a result, materials that may have advantageous properties as lower electrodes may be utilized despite the fact that they may be sensitive to subsequent processing steps or the open environment.

20. 发明申请

US20080054342A1 Memory array having floating gate semiconductor device 失效
标题翻译：具有浮置栅极半导体器件的存储器阵列
公开(公告)号：US20080054342A1
公开(公告)日：2008-03-06
申请号：US11933728
申请日：2007-11-01
申请人： Trung Doan , Tyler Lowrey
发明人： Trung Doan , Tyler Lowrey
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42336 , H01L29/7881
摘要： A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.
摘要翻译：提供了一种用于形成诸如电可擦除可编程只读存储器的浮置栅极半导体器件的方法。该器件包括具有电隔离的有源区的硅衬底。栅极氧化物以及FET的其它部件（例如，源极，漏极）形成在有源区域中。通过将导电层（例如多晶硅）沉积到栅极氧化物上而形成自对准浮栅。然后将导电层化学机械平面化到隔离层的端点，使得去除凹部中和栅极氧化物上的材料以外的所有导电层。在形成浮栅之后，在浮栅上形成绝缘层，在绝缘层上形成控制栅。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式