专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07902536B2 Memory device and method of making same 有权
标题翻译：存储器件及其制作方法
公开(公告)号：US07902536B2
公开(公告)日：2011-03-08
申请号：US11495927
申请日：2006-07-28
申请人： Wolodymyr Czubatyj , Tyler Lowrey , Sergey Kostylev
发明人： Wolodymyr Czubatyj , Tyler Lowrey , Sergey Kostylev
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： G11C11/5678 , G11C11/56 , G11C13/0004 , H01L45/06 , H01L45/122 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a substantially planar first area of electrical communication with the phase-change material. The radial memory device also includes a second electrode in electrical communication with the phase-change material, the second electrode having a second area of electrical communication with the phase-change material, the second area being laterally spacedly disposed from the first area and substantially circumscribing the first area.Further, a method of making a memory device is disclosed. The steps include depositing a first electrode, depositing a first insulator, configuring the first insulator to define a first opening. The first opening provides for a generally planar first contact of the first electrode. The method further including the steps of depositing a phase-change material, depositing a second insulator, configuring the second insulator, depositing a second electrode having a second contact laterally displaced from said first contact, and configuring said second electrode.
摘要翻译：径向存储器件包括相变材料，与相变材料电连通的第一电极，第一电极具有与相变材料电连通的基本平坦的第一区域。所述径向存储装置还包括与所述相变材料电连通的第二电极，所述第二电极具有与所述相变材料电连通的第二区域，所述第二区域与所述第一区域横向间隔设置并且基本上限定第一个区域。此外，公开了一种制造存储器件的方法。这些步骤包括沉积第一电极，沉积第一绝缘体，构成第一绝缘体以限定第一开口。第一开口提供第一电极的大致平面的第一接触。该方法还包括以下步骤：沉积相变材料，沉积第二绝缘体，构成第二绝缘体，沉积具有从所述第一触点横向移位的第二触点的第二电极，以及配置所述第二电极。

2. 发明申请

US20080273372A1 Method of Programming Multi-Layer Chalcogenide Devices 有权
标题翻译：多层硫族化物器件编程方法
公开(公告)号：US20080273372A1
公开(公告)日：2008-11-06
申请号：US12178148
申请日：2008-07-23
申请人： Regino Sandoval , Sergey A. Kostylev , Wolodymyr Czubatyj , Tyler Lowrey
发明人： Regino Sandoval , Sergey A. Kostylev , Wolodymyr Czubatyj , Tyler Lowrey
IPC分类号： G11C11/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625
摘要： A method of programming a multi-layer chalcogenide electronic device. The device includes an active region in electrical communication with two terminals, where the active region includes two or more layers. The method includes providing an electrical signal between the two terminals, where the electrical signal alters an electrical characteristic of a layer remote from one of the terminals. In one embodiment, the layer remote from the terminal is a chalcogenide material and the electrical characteristic is resistance. In another embodiment, an electrical characteristic of the layer in contact with the terminal is also altered. The alteration of an electrical characteristic may be caused by a transformation of a chalcogenide material from one structural state to another structural state.
摘要翻译：一种编程多层硫族化物电子器件的方法。该器件包括与两个端子电连通的有源区域，其中有源区域包括两层或更多层。该方法包括在两个终端之间提供电信号，其中电信号改变远离一个终端的层的电特性。在一个实施例中，远离终端的层是硫族化物材料，并且电特性是电阻。在另一个实施例中，与终端接触的层的电特性也被改变。电特性的改变可能是由硫族化物材料从一种结构状态转变为另一种结构状态引起的。

3. 发明申请

US20080224120A1 Phase change device with offset contact 有权
标题翻译：相移装置，带偏置接点
公开(公告)号：US20080224120A1
公开(公告)日：2008-09-18
申请号：US12152330
申请日：2008-05-14
申请人： Wolodymyr Czubatyj , Tyler Lowrey
发明人： Wolodymyr Czubatyj , Tyler Lowrey
IPC分类号： H01L45/00
CPC分类号： H01L45/126 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/141
摘要： A programmable resistance memory combines multiple cells into a block that includes one or more shared electrodes. The shared electrode configuration provides additional thermal isolation for the active region of each memory cell, thereby reducing the current required to program each memory cell.
摘要翻译：可编程电阻存储器将多个单元组合成包括一个或多个共享电极的块。共享电极配置为每个存储单元的有源区域提供额外的热隔离，从而减少编程每个存储单元所需的电流。

4. 发明申请

US20080042119A1 Multi-layered chalcogenide and related devices having enhanced operational characteristics 审中-公开
标题翻译：具有增强的操作特性的多层硫族化物和相关装置
公开(公告)号：US20080042119A1
公开(公告)日：2008-02-21
申请号：US11821246
申请日：2007-06-22
申请人： Regino Sandoval , Wolodymyr Czubatyj , Tyler Lowrey , Isamu Asano
发明人： Regino Sandoval , Wolodymyr Czubatyj , Tyler Lowrey , Isamu Asano
IPC分类号： H01L47/00
CPC分类号： H01L45/1246 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625
摘要： A multi-layer chalcogenide, memory or switching device. The device includes an active region disposed between a first terminal and a second terminal. The active region includes a first layer and a second layer, where one of the layers is a heterogeneous layer that includes an operational component and a promoter component. The other layer may be a homogeneous or heterogeneous layer. In exemplary embodiments, the operational component is a chalcogenide or phase change material and the promoter component is an insulating or dielectric material. Inclusion of the promoter component provides beneficial performance characteristics such as a reduction in reset current or minimization of formation requirements.
摘要翻译：多层硫族化物，记忆体或开关装置。该装置包括设置在第一端子和第二端子之间的有源区域。有源区包括第一层和第二层，其中一层是包含可操作组分和促进剂组分的异质层。另一层可以是均质或非均质层。在示例性实施方案中，操作组分是硫族化物或相变材料，并且促进剂组分是绝缘或介电材料。包含启动子组分提供了有益的性能特征，例如复位电流的降低或形成要求的最小化。

5. 发明申请

US20080023685A1 MEMORY DEVICE AND METHOD OF MAKING SAME 审中-公开
标题翻译：存储器件及其制造方法
公开(公告)号：US20080023685A1
公开(公告)日：2008-01-31
申请号：US11743459
申请日：2007-05-02
申请人： Wolodymyr Czubatyj , Tyler Lowrey , Sergey Kostylev , Regino Sandoval
发明人： Wolodymyr Czubatyj , Tyler Lowrey , Sergey Kostylev , Regino Sandoval
IPC分类号： H01L47/00
CPC分类号： H01L45/148 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/1246 , H01L45/143 , H01L45/144
摘要： A memory device includes a phase-change material and a first electrode in electrical communication with the phase-change material. Also included is a second electrode in electrical communication with the phase-change material and a dielectric layer. The dielectric layer is disposed between the first electrode and the second electrode. The dielectric layer has an opening therethrough. The phase-change material is disposed on both sides of the dielectric layer and within the opening. Electrical communication within the device is by means of virtual contacts.
摘要翻译：存储器件包括相变材料和与相变材料电连通的第一电极。还包括与相变材料和介电层电连通的第二电极。介电层设置在第一电极和第二电极之间。电介质层具有通过其的开口。相变材料设置在电介质层的两侧和开口内。设备内的电气通信是通过虚拟接触。

6. 发明申请

US20070096074A1 Electrically rewritable non-volatile memory element and method of manufacturing the same 有权
标题翻译：电可重写非易失性存储元件及其制造方法
公开(公告)号：US20070096074A1
公开(公告)日：2007-05-03
申请号：US11264129
申请日：2005-11-02
申请人： Isamu Asano , Natsuki Sato , Tyler Lowrey , Guy Wicker , Wolodymyr Czubatyj , Stephen Hudgens
发明人： Isamu Asano , Natsuki Sato , Tyler Lowrey , Guy Wicker , Wolodymyr Czubatyj , Stephen Hudgens
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148
摘要： A non-volatile memory element includes a first interlayer insulation layer 11 having a first through-hole 11a, a second interlayer insulation layer 12 having a second through-hole 12a formed on the first interlayer insulation layer 11, a bottom electrode 13 provided in the first through-hole 11, recording layer 15 containing phase change material provided in the second through-hole 12, a top electrode 16 provided on the second interlayer insulation layer 12, and a thin-film insulation layer 14 formed between the bottom electrode 13 and the recording layer 15. In accordance with this invention, the diameter D1 of a bottom electrode 13 buried in a first through-hole 11a is smaller than the diameter D2 of a second through-hole 12a, thereby decreasing the thermal capacity of the bottom electrode 13. Therefore, when a pore 14a is formed by dielectric breakdown in a thin-film insulation layer 14 and the vicinity is used as a heating region, the amount of heat escaping to the bottom electrode 13 is decreased, resulting in higher heating efficiency.
摘要翻译：非易失性存储元件包括具有第一通孔11a的第一层间绝缘层11，具有形成在第一层间绝缘层11上的第二通孔12a的第二层间绝缘层12，在第一通孔11中，设置在第二通孔12中的包含相变材料的记录层15，设置在第二层间绝缘层12上的顶部电极16和形成在第二通孔12的底部电极之间的薄膜绝缘层14 13和记录层15。根据本发明，埋在第一通孔11a中的底部电极13的直径D 1小于第二通孔12a的直径D 2，从而降低底部电极13的热容量。因此，当通过薄膜绝缘层14中的电介质击穿形成孔14a并且将其附近用作加热区域时，逸出到底部电极13的热量减少，导致更高的加热效率。

7. 发明授权

US08363446B2 Multilevel variable resistance memory cell utilizing crystalline programming states 有权
标题翻译：利用晶体编程状态的多电平可变电阻存储单元
公开(公告)号：US08363446B2
公开(公告)日：2013-01-29
申请号：US12578638
申请日：2009-10-14
申请人： Wolodymyr Czubatyj , Tyler Lowrey , Charles Dennison , Carl Schell
发明人： Wolodymyr Czubatyj , Tyler Lowrey , Charles Dennison , Carl Schell
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0092
摘要： A method of programming an electrical variable resistance memory device. When applied to variable resistance memory devices that incorporate a phase-change material as the active material, the method utilizes a plurality of crystalline programming states. The crystalline programming states are distinguishable on the basis of resistance, where the resistance values of the different states are stable with time and exhibit little or no drift. As a result, the programming scheme is particularly suited to multilevel memory applications. The crystalline programming states may be achieved by stabilizing crystalline phases that adopt different crystallographic structures or by stabilizing crystalline phases that include mixtures of two or more distinct crystallographic structures that vary in the relative proportions of the different crystallographic structures. The programming scheme incorporates at least two crystalline programming states and further includes at least a third programming state that may be a crystalline, amorphous or mixed crystalline-amorphous state.
摘要翻译：一种编程电可变电阻存储器件的方法。当应用于包含相变材料作为活性材料的可变电阻存储器件时，该方法利用多个晶体编程状态。结晶编程状态可以根据电阻进行区分，其中不同状态的电阻值随时间稳定并且表现出很小的或没有漂移。因此，编程方案特别适用于多层存储器应用。晶体编程状态可以通过稳定采用不同晶体结构的结晶相或通过稳定结晶相来实现，所述结晶相包括两种或更多种不同结晶学结构的混合物，其在不同结晶学结构的相对比例中变化。编程方案包含至少两个晶体编程状态，并且还包括至少第三编程状态，其可以是晶体，无定形或混合晶体 - 非晶状态。

8. 发明授权

US08344350B2 Phase change device with offset contact 有权
标题翻译：相移装置，带偏置接点
公开(公告)号：US08344350B2
公开(公告)日：2013-01-01
申请号：US13093109
申请日：2011-04-25
申请人： Wolodymyr Czubatyj , Tyler Lowrey
发明人： Wolodymyr Czubatyj , Tyler Lowrey
IPC分类号： H01L21/06 , H01L45/00
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/126
摘要： A programmable resistance memory combines multiple cells into a block that includes one or more shared electrodes. The shared electrode configuration provides additional thermal isolation for the active region of each memory cell, thereby reducing the current required to program each memory cell.
摘要翻译：可编程电阻存储器将多个单元组合成包括一个或多个共享电极的块。共享电极配置为每个存储单元的有源区域提供额外的热隔离，从而减少编程每个存储单元所需的电流。

9. 发明申请

US20100321991A1 Chalcogenide Devices Exhibiting Stable Operation from the As-Fabricated State 审中-公开
标题翻译：从制造国展示稳定运行的硫族化物装置
公开(公告)号：US20100321991A1
公开(公告)日：2010-12-23
申请号：US12871975
申请日：2010-08-31
申请人： Sergey A. Kostylev , Tyler Lowrey , Guy Wicker , Wolodymyr Czubatyj
发明人： Sergey A. Kostylev , Tyler Lowrey , Guy Wicker , Wolodymyr Czubatyj
IPC分类号： G11C11/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625
摘要： A chalcogenide material and chalcogenide memory device having less stringent requirements for formation, improved thermal stability and/or faster operation. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. Electrical devices containing the instant chalcogenide materials show a rapid convergence of the set resistance during cycles of setting and resetting the device from its as-fabricated state, thus leading to a reduced or eliminated need to subject the device to post-fabrication electrical formation prior to end-use operation. Improved thermal stability is manifested in terms of prolonged stability of the resistance of the device at elevated temperatures, which leads to an inhibition of thermally induced setting of the reset state in the device. Significant improvements in the 10 year data retention temperature are demonstrated. Faster device operation is achieved through an increased speed of crystallization, which acts to shorten the time required to transform the chalcogenide material from its reset state to its set state in an electrical memory device.
摘要翻译：一种硫族化物材料和硫族化物记忆装置，其对形成，改进的热稳定性和/或更快的操作要求不太严格。硫属化物材料包括Ge，Sb和Te的材料，其中Ge和/或Te含量相对于通常使用的Ge 2 Sb 2 Te 5硫族化物组合物是稀的。包含瞬时硫族化物材料的电气装置显示设定循环期间的设定电阻的快速收敛以及将器件从其制造状态复位，从而导致减少或消除了将器件置于后制造电形成之前最终使用操作。改进的热稳定性表现在器件在升高的温度下的电阻的延长的稳定性，这导致抑制器件中复位状态的热诱导设置。展示了10年数据保存温度的显着改进。通过提高结晶速度实现更快的器件操作，其用于缩短将硫族化物材料从其复位状态转换到其在电存储器件中的设定状态所需的时间。

10. 发明申请

US20090298222A1 Method for manufacturing Chalcogenide devices 审中-公开
标题翻译：制造硫族化物装置的方法
公开(公告)号：US20090298222A1
公开(公告)日：2009-12-03
申请号：US12154952
申请日：2008-05-28
申请人： Tyler Lowrey , Jeff Fournier , Robert Nuss , Carl Schell , Guy Wicker , Jim Ricker , James Reed , Ed Spall , Sergey Kostylev , Wolodymyr Czubatyj , Regino Sandoval
发明人： Tyler Lowrey , Jeff Fournier , Robert Nuss , Carl Schell , Guy Wicker , Jim Ricker , James Reed , Ed Spall , Sergey Kostylev , Wolodymyr Czubatyj , Regino Sandoval
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L45/04 , H01L45/144 , H01L45/1608
摘要： A method of chalcogenide device formation includes treatment of the surface upon which the chalcogenide material is deposited. The treatment reduces or eliminates native oxides and other contaminants from the surface, thereby increasing the adhesion of the chalcogenide layer to the treated surface, eliminating voids between the chalcogenide layer and deposition surface and reducing the degradation of chalcogenide material due to the migration of contaminants into the chalcogenide.
摘要翻译：硫族化物器件形成的方法包括处理沉积硫族化物材料的表面。该处理减少或消除了表面的天然氧化物和其他污染物，从而增加了硫属化物层与处理过的表面的粘附性，消除了硫属化物层与沉积表面之间的空隙，并且由于污染物的迁移而降低了硫族化物材料的降解硫族化物。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式