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1. 发明授权

US08908413B2 Programmable resistance memory 有权
标题翻译：可编程电阻记忆
公开(公告)号：US08908413B2
公开(公告)日：2014-12-09
申请号：US13216675
申请日：2011-08-24
申请人： Tyler Lowrey , Carl Schell , Wally Czubatyj , Steve Hudgens , Jon Maimon , Jeff Fournier , Mike Hennessey , Ed Spall
发明人： Tyler Lowrey , Carl Schell , Wally Czubatyj , Steve Hudgens , Jon Maimon , Jeff Fournier , Mike Hennessey , Ed Spall
IPC分类号： G11C11/00 , G11C11/56 , G11C13/00
CPC分类号： G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/0035
摘要： A memory includes a programmable resistance array with high ratio of dynamic range to drift coefficient phase change memory devices.
摘要翻译：存储器包括具有高比例的动态范围与漂移系数相变存储器件的可编程电阻阵列。

2. 发明授权

US08513576B2 Dual resistance heater for phase change devices and manufacturing method thereof 有权
公开(公告)号：US08513576B2
公开(公告)日：2013-08-20
申请号：US12980141
申请日：2010-12-28
申请人： Yudong Kim , Ilya V. Karpov , Charles C. Kuo , Greg Atwood , Maria Santina Marangon , Tyler Lowrey
发明人： Yudong Kim , Ilya V. Karpov , Charles C. Kuo , Greg Atwood , Maria Santina Marangon , Tyler Lowrey
IPC分类号： H05B1/02 , B23K9/00 , G11C11/00 , H01L29/04 , H01C7/06 , H01C7/00
CPC分类号： H01L45/16 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/141 , H01L45/1683
摘要： A dual resistance heater for a phase change material region is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface of the heater material relative to the remainder of the heater material. As a result, the portion of the heater material approximate to the phase change material region is a highly effective heater because of its high resistance, but the bulk of the heater material is not as resistive and, thus, does not increase the voltage drop and the current usage of the device.

3. 发明授权

US08379439B2 Programmable matrix array with chalcogenide material 有权
标题翻译：具有硫属化物材料的可编程矩阵阵列
公开(公告)号：US08379439B2
公开(公告)日：2013-02-19
申请号：US12640723
申请日：2009-12-17
申请人： Tyler Lowrey , Ward Parkinson , Guy Wicker
发明人： Tyler Lowrey , Ward Parkinson , Guy Wicker
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/76 , G11C2213/77 , H01L27/2427 , H01L45/04 , H01L45/1233 , H01L45/141
摘要： A memory element, a threshold switching element, or the series combination of a memory element and a threshold switching element may be used for coupling conductive lines in an electrically programmable matrix array. Leakage may be reduced by optionally placing a breakdown layer in series with the phase-change material and/or threshold switching material between the conductive lines. The matrix array may be used in a programmable logic device.
摘要翻译：可以使用存储元件，阈值开关元件或存储元件和阈值开关元件的串联组合来耦合电可编程矩阵阵列中的导线。可以通过选择性地将导电线之间的相变材料和/或阈值开关材料串联的击穿层来降低泄漏。矩阵阵列可以用在可编程逻辑器件中。

4. 发明授权

US08363458B2 Memory controller 有权
公开(公告)号：US08363458B2
公开(公告)日：2013-01-29
申请号：US12157083
申请日：2008-06-06
申请人： Tyler Lowrey
发明人： Tyler Lowrey
IPC分类号： G11C11/00
CPC分类号： G11C5/025 , G11C5/02 , G11C8/10 , G11C13/0004 , G11C13/003 , G11C2213/52 , G11C2213/71
摘要： A memory controller provides interfaces for one or more thin film memory circuits. The controller may include an analog interface for one or more thin film memories. Such an analog interface may accept analog signals representative of an associated thin film memory's memory state, condition and sense the signal, and encode the signal into a digital value.

5. 发明申请

US20110168964A1 Processing Phase Change Material to Improve Programming Speed 有权
标题翻译：处理相变材料以提高编程速度
公开(公告)号：US20110168964A1
公开(公告)日：2011-07-14
申请号：US13004167
申请日：2011-01-11
申请人： Stephen J. Hudgens , Tyler Lowrey
发明人： Stephen J. Hudgens , Tyler Lowrey
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1625 , H01L45/165 , H01L45/1658
摘要： A phase change material may be processed to reduce its microcrystalline grain size and may also be processed to increase the crystallization or set programming speed of the material. For example, material doped with nitrogen to reduce grain size may be doped with titanium to reduce crystallization time.
摘要翻译：可以处理相变材料以降低其微晶粒度，并且还可以加工以增加材料的结晶或设定编程速度。例如，掺杂氮以减小晶粒尺寸的材料可以掺杂钛以减少结晶时间。

6. 发明授权

US07978506B2 Thin film logic device and system 有权
标题翻译：薄膜逻辑器件和系统
公开(公告)号：US07978506B2
公开(公告)日：2011-07-12
申请号：US12157049
申请日：2008-06-06
申请人： Tyler Lowrey
发明人： Tyler Lowrey
IPC分类号： G11C11/00
CPC分类号： H03K19/1733
摘要： Thin film logic circuits employ thin-film switching devices to execute complementary logic functions. Such logic devices operate, as complementary metal oxide semiconductor (CMOS) logic devices do, in a manner that does not provide a direct conduction path between a system supply and a system return. Complementary logic circuits may employ three-terminal threshold switches as switching elements.
摘要翻译：薄膜逻辑电路采用薄膜开关器件来执行互补的逻辑功能。作为互补金属氧化物半导体（CMOS）逻辑器件，这样的逻辑器件以不提供系统电源和系统返回之间的直接传导路径的方式工作。互补逻辑电路可以采用三端口阈值开关作为开关元件。

7. 发明授权

US07969769B2 Multi-terminal chalcogenide logic circuits 有权
标题翻译：多端硫族化物逻辑电路
公开(公告)号：US07969769B2
公开(公告)日：2011-06-28
申请号：US11724485
申请日：2007-03-15
申请人： Tyler Lowrey
发明人： Tyler Lowrey
IPC分类号： G11C11/00
CPC分类号： H03K19/1733
摘要： Logic circuits are disclosed that include one or more three-terminal chalcogenide devices. The three-terminal chalcogenide devices are electrically interconnected and configured to perform one or more logic operations, including AND, OR, NOT, NAND, NOR, XOR, and XNOR. Embodiments include series and parallel configurations of three-terminal chalcogenide devices. The chalcogenide devices include a chalcogenide switching material as the working medium along with three electrical terminals in electrical communication therewith.In one embodiment, the circuits include one or more input terminals, one or more output terminals, and a clock terminal. The input terminals receive one or more input signals and deliver them to the circuit for processing according to a logic operation. Upon conclusion of processing, the output of the circuit is provided to the output terminal. The clock terminal delivers a clock signal to facilitate operation of the three-terminal devices included in the instant circuits. In one embodiment, the clock signal includes an ON cycle and an OFF cycle, where the circuit performs a logic operation during the ON cycle and any three-terminal devices that are switched to the conductive state during the ON cycle are returned to their resistive state during the OFF cycle.
摘要翻译：公开了包括一个或多个三末端硫族化物装置的逻辑电路。三端硫属化物器件电互连并被配置为执行一个或多个逻辑操作，包括AND，OR，NOT，NAND，NOR，XOR和XNOR。实施方案包括三末端硫族化物装置的串联和并联配置。硫族化物装置包括作为工作介质的硫族化物转换材料以及与其电连通的三个电端子。在一个实施例中，电路包括一个或多个输入端子，一个或多个输出端子和时钟端子。输入端子接收一个或多个输入信号，并根据逻辑运算将它们传送到电路进行处理。在处理结束时，将电路的输出提供给输出端。时钟终端提供时钟信号，以便于即时电路中包括的三端设备的操作。在一个实施例中，时钟信号包括ON周期和OFF周期，其中电路在ON周期期间执行逻辑运算，并且在ON周期期间切换到导通状态的任何三端器件返回到其电阻状态在OFF循环期间。

8. 发明授权

US07902536B2 Memory device and method of making same 有权
标题翻译：存储器件及其制作方法
公开(公告)号：US07902536B2
公开(公告)日：2011-03-08
申请号：US11495927
申请日：2006-07-28
申请人： Wolodymyr Czubatyj , Tyler Lowrey , Sergey Kostylev
发明人： Wolodymyr Czubatyj , Tyler Lowrey , Sergey Kostylev
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： G11C11/5678 , G11C11/56 , G11C13/0004 , H01L45/06 , H01L45/122 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a substantially planar first area of electrical communication with the phase-change material. The radial memory device also includes a second electrode in electrical communication with the phase-change material, the second electrode having a second area of electrical communication with the phase-change material, the second area being laterally spacedly disposed from the first area and substantially circumscribing the first area.Further, a method of making a memory device is disclosed. The steps include depositing a first electrode, depositing a first insulator, configuring the first insulator to define a first opening. The first opening provides for a generally planar first contact of the first electrode. The method further including the steps of depositing a phase-change material, depositing a second insulator, configuring the second insulator, depositing a second electrode having a second contact laterally displaced from said first contact, and configuring said second electrode.
摘要翻译：径向存储器件包括相变材料，与相变材料电连通的第一电极，第一电极具有与相变材料电连通的基本平坦的第一区域。所述径向存储装置还包括与所述相变材料电连通的第二电极，所述第二电极具有与所述相变材料电连通的第二区域，所述第二区域与所述第一区域横向间隔设置并且基本上限定第一个区域。此外，公开了一种制造存储器件的方法。这些步骤包括沉积第一电极，沉积第一绝缘体，构成第一绝缘体以限定第一开口。第一开口提供第一电极的大致平面的第一接触。该方法还包括以下步骤：沉积相变材料，沉积第二绝缘体，构成第二绝缘体，沉积具有从所述第一触点横向移位的第二触点的第二电极，以及配置所述第二电极。

9. 发明授权

US07880123B2 Dual resistance heater for phase change devices and manufacturing method thereof 有权
标题翻译：用于相变装置的双电阻加热器及其制造方法
公开(公告)号：US07880123B2
公开(公告)日：2011-02-01
申请号：US11312231
申请日：2005-12-19
申请人： Yudong Kim , Ilya V. Karpov , Charles C. Kuo , Greg Atwood , Maria Santina Marangon , Tyler Lowrey
发明人： Yudong Kim , Ilya V. Karpov , Charles C. Kuo , Greg Atwood , Maria Santina Marangon , Tyler Lowrey
IPC分类号： H05B1/02
CPC分类号： H01L45/16 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/141 , H01L45/1683
摘要： A dual resistance heater for a phase change material region is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface of the heater material relative to the remainder of the heater material. As a result, the portion of the heater material approximate to the phase change material region is a highly effective heater because of its high resistance, but the bulk of the heater material is not as resistive and, thus, does not increase the voltage drop and the current usage of the device.
摘要翻译：通过沉积电阻材料形成用于相变材料区域的双电阻加热器。然后将加热器材料暴露于植入或等离子体，这增加了加热器材料表面相对于加热器材料的剩余部分的电阻。结果，由于加热材料的高电阻，加热器材料的部分接近相变材料区域是高效的加热器，而是加热器材料的体积不是电阻的，因此不会增加电压降，当前使用的设备。

10. 发明申请

US20100054030A1 Programmable resistance memory 有权
标题翻译：可编程电阻记忆
公开(公告)号：US20100054030A1
公开(公告)日：2010-03-04
申请号：US12229997
申请日：2008-08-28
申请人： Tyler Lowrey
发明人： Tyler Lowrey
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00 , H01L21/00
CPC分类号： G11C13/0004 , G11C2213/72
摘要： A memory includes a programmable resistance array and unipolar MOS peripheral circuitry. The peripheral circuitry includes address decoding circuitry. Because unipolar MOS circuitry is employed, the number of mask steps and, concomitantly, the cost of the programmable resistance memory may be minimized.
摘要翻译：存储器包括可编程电阻阵列和单极MOS外围电路。外围电路包括地址解码电路。因为采用单极MOS电路，所以可以将屏蔽步骤的数量以及伴随的可编程电阻存储器的成本最小化。

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