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11. 发明申请

US20150188495A1 CURRENT CONTROLLED TRANSCONDUCTING INVERTING AMPLIFIERS 有权
标题翻译：电流控制转换放大器
公开(公告)号：US20150188495A1
公开(公告)日：2015-07-02
申请号：US14150014
申请日：2014-01-08
申请人： Cambridge Silicon Radio Limited
发明人： Michael John Story
IPC分类号： H03F1/02 , H03M1/18 , H03M1/00 , H03F3/16 , H03F3/193
CPC分类号： H03F1/0211 , H03F1/308 , H03F1/523 , H03F1/526 , H03F3/16 , H03F3/193 , H03F3/3028 , H03F3/3061 , H03F3/72 , H03F2200/129 , H03F2200/144 , H03F2200/294 , H03F2203/30031 , H03F2203/30084 , H03F2203/30117 , H03M1/002 , H03M1/18 , H03M1/66 , H03M3/40 , H03M3/43 , H03M3/438
摘要： An amplifier including a first transistor of a first conduction type; a second transistor of a second conduction type, the second transistor being coupled to the first transistor; an input for receiving an input signal, a control terminal of the first transistor being coupled to a control terminal of the second transistor, the control terminals being coupled to the input; an output for outputting an output signal, the output being coupled to the first transistor and the second transistor; and a current supply coupled to the first transistor and configured to supply current so as to cause a predetermined transconductance of the amplifier.
摘要翻译：一种放大器，包括第一导电类型的第一晶体管; 第二导体类型的第二晶体管，所述第二晶体管耦合到所述第一晶体管; 用于接收输入信号的输入端，所述第一晶体管的控制端子耦合到所述第二晶体管的控制端子，所述控制端子耦合到所述输入端; 用于输出输出信号的输出，所述输出耦合到所述第一晶体管和所述第二晶体管; 以及电流源，耦合到第一晶体管并且被配置为提供电流以便引起放大器的预定跨导。

12. 发明申请

US20150188407A1 VOLTAGE REGULATOR 有权
标题翻译：电压稳压器
公开(公告)号：US20150188407A1
公开(公告)日：2015-07-02
申请号：US14143150
申请日：2013-12-30
申请人： Cambridge Silicon Radio Limited
发明人： Barnaby Golder , Peter Andrew Rees Williams , Sukanta Kishore Panigrahi , Timothy Charles Clapp , Richard Andrew Wilkinson
IPC分类号： H02M1/088 , H02J1/00 , H02M3/158
CPC分类号： H02M1/088 , H02J1/00 , H02M3/158 , H02M3/1582 , H02M2001/0003 , H02M2001/009 , Y10T307/406
摘要： A method of operating a voltage regulator including a source voltage rail and a plurality of output voltage rails, the method including: converting a source voltage on the source voltage rail to a respective output voltage on each output voltage rail; selecting an output voltage rail; comparing the output voltage on the selected output voltage rail to a reference voltage for the selected output voltage rail; and if the output voltage of the selected output voltage rail is less than the reference voltage for the selected output voltage rail, controlling the voltage regulator to increase the output voltage on the selected output voltage rail, wherein the frequency at which an output voltage rail is selected is dependent upon the rate at which the voltage regulator has previously increased the output voltage on that output voltage rail.
摘要翻译：一种操作包括源极电压轨道和多个输出电压轨道的电压调节器的方法，所述方法包括：将源极电压轨上的源极电压转换为每个输出电压轨上的相应输出电压; 选择输出电压轨; 将所选输出电压轨上的输出电压与所选输出电压轨的参考电压进行比较; 并且如果所选择的输出电压轨的输出电压小于所选择的输出电压轨的参考电压，则控制电压调节器增加所选输出电压轨上的输出电压，其中输出电压轨为选择取决于电压调节器先前增加该输出电压轨上的输出电压的速率。

13. 发明申请

US20150186289A1 CACHE ARCHITECTURE 审中-公开
标题翻译：缓存架构
公开(公告)号：US20150186289A1
公开(公告)日：2015-07-02
申请号：US14141009
申请日：2013-12-26
申请人： Cambridge Silicon Radio Limited
发明人： Paul Hoayun
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0866 , G06F2212/202 , G06F2212/222 , Y02D10/13
摘要： A cache controller for a processing system, the cache controller being capable of providing an interface between a data requester and a plurality of memories including a first memory, a second memory and a cache memory, the cache controller being configured to, in response to receiving a request for data at a specified address in a specified memory, perform the steps of: determining whether either (a) a data field in the cache memory that corresponds to the specified address has been populated from the specified memory or (b) the specified memory is the first memory and the data field corresponding to the specified address in the cache memory has been populated from the second memory; and if that determination is positive, responding to the request by providing the content of the data field in the cache memory corresponding to the specified address.
摘要翻译：一种用于处理系统的高速缓存控制器，所述高速缓存控制器能够在数据请求器和包括第一存储器，第二存储器和高速缓冲存储器的多个存储器之间提供接口，所述高速缓存控制器被配置为响应于接收在指定的存储器中的指定地址处的数据请求，执行以下步骤：确定是否（a）与指定地址对应的高速缓冲存储器中的数据字段已经从指定的存储器填充，或者（b）指定的存储器是第一存储器，并且与缓冲存储器中的指定地址相对应的数据字段已经从第二存储器填充; 并且如果该确定是肯定的，则通过提供与指定地址相对应的高速缓冲存储器中的数据字段的内容来响应该请求。

14. 发明授权

US09058888B2 Control circuitry for memory cells 有权
标题翻译：存储单元的控制电路
公开(公告)号：US09058888B2
公开(公告)日：2015-06-16
申请号：US13494283
申请日：2012-06-12
申请人： Luca Milani , Kwangseok Han , Rainer Herberholz , Justin Penfold
发明人： Luca Milani , Kwangseok Han , Rainer Herberholz , Justin Penfold
IPC分类号： G11C19/08 , G11C17/18 , G11C16/04 , G11C29/02 , G11C29/00 , H01L27/112 , G11C17/14 , G11C29/04 , G11C29/50
CPC分类号： G11C17/18 , G11C16/0475 , G11C17/14 , G11C17/146 , G11C29/027 , G11C29/785 , G11C2029/0409 , G11C2029/5006 , H01L27/11206
摘要： Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown detection circuit is connected between the device being programmed and ground and comprises three transistors, at least one of which is capable of withstanding the programming voltage in case of breakdown. Other embodiments describe a flag bit cell design, a memory array and methods of reading and writing from/to that array, and circuitry for biasing a memory word-line for both read and write operations. The embodiments may be used separately or in a combination.
摘要翻译：描述了存储器单元的控制电路。在一个实施例中，描述了击穿检测电路，其被布置成通过监视击穿检测电路中的端子处的阻抗电平来检测指示存储器单元编程期间的有缺陷单元的异常高电流。故障检测电路连接在被编程和接地的器件之间，并且包括三个晶体管，其中至少一个能够在击穿的情况下承受编程电压。其他实施例描述了标志位单元设计，存储器阵列以及从该阵列读取和写入方法以及用于偏置读取和写入操作的存储器字线的电路。实施例可以单独使用或组合使用。

15. 发明授权

US09048938B2 Chirp communications 有权
标题翻译：啁啾通信
公开(公告)号：US09048938B2
公开(公告)日：2015-06-02
申请号：US13451505
申请日：2012-04-19
申请人： Paul Dominic Hiscock
发明人： Paul Dominic Hiscock
IPC分类号： H04B1/00 , H04B1/713
CPC分类号： H04B1/713 , H04L27/10 , H04L27/103
摘要： A method for receiving chirp signals at a receiver device according to a protocol in which each chirp signal has a gradient known to the receiver device, the method comprising: receiving a chirp signal having a first gradient g; generating a reference chirp signal having a second gradient g′, wherein the second gradient g′ differs from the first gradient g by a fixed value v; multiplying the reference chirp signal and the received chirp signal so as to form a mixed chirp signal; and detecting the received chirp signal by correlating the mixed chirp signal with a fixed gradient correlating chirp signal.
摘要翻译：一种用于根据协议在接收机设备处接收啁啾信号的方法，其中每个啁啾信号具有接收机设备已知的梯度，该方法包括：接收具有第一梯度g的线性调频信号; 生成具有第二梯度g'的参考线性调频信号，其中第二梯度g'与第一梯度g不同固定值v; 乘以基准线性调频脉冲信号和接收线性调频脉冲信号，形成混合啁啾信号; 以及通过将混合啁啾信号与固定梯度相关啁啾信号相关联来检测接收到的啁啾信号。

16. 发明授权

US09041475B1 Thermally stable low power chip clocking 有权
标题翻译：热稳定的低功耗芯片时钟
公开(公告)号：US09041475B1
公开(公告)日：2015-05-26
申请号：US14141730
申请日：2013-12-27
申请人： Cambridge Silicon Radio Limited
发明人： Peter Andrew Rees Williams
IPC分类号： H03B5/12 , H03L5/00
CPC分类号： H03L1/02
摘要： A method of controlling an integrated circuit chip including first and second clock sources, the first clock source being more thermally stable and having a higher power consumption, the integrated circuit chip being operable in a first mode in which the first clock source is inactive and the second clock source active and in a second mode in which the first and second clock sources are active, the method including operating the integrated circuit chip in the first mode; taking a measurement indicative of temperature; if the measurement indicates that the temperature is outside of a temperature band: activating the first clock source so as to operate the integrated circuit chip in the second mode; recalibrating the second clock source against the first clock source; and following the recalibration, deactivating the first clock source so as to return the integrated circuit chip to the first mode.
摘要翻译：一种控制包括第一和第二时钟源的集成电路芯片的方法，所述第一时钟源更加热稳定并且具有更高的功率消耗，所述集成电路芯片可操作在第一模式中，其中所述第一时钟源不活动，第二时钟源是有效的，并且在第一和第二时钟源有效的第二模式中，所述方法包括以第一模式操作集成电路芯片; 测量温度; 如果测量指示温度在温度带之外;激活第一时钟源，以便在第二模式下操作集成电路芯片; 根据第一时钟源重新校准第二时钟源; 并且在重新校准之后，去激活第一时钟源，以使集成电路芯片返回到第一模式。

17. 发明申请

US20150140937A1 ON-CHIP TRANSMIT AND RECEIVE FILTERING 审中-公开
标题翻译：片上发送和接收过滤
公开(公告)号：US20150140937A1
公开(公告)日：2015-05-21
申请号：US14150145
申请日：2014-01-08
申请人： Cambridge Silicon Radio Limited
发明人： Michael John Story , Terence Chi-Fung Kwok
IPC分类号： H04B1/44 , H04W52/02 , H04B1/38
CPC分类号： H04B1/44 , H04B1/3833 , H04B1/525 , H04W52/028 , Y02D70/00 , Y02D70/144 , Y02D70/40
摘要： An integrated circuit chip including a chip pin configured to direct radio frequency signals on and off chip; a signal path from the chip pin which divides into a first signal path coupled to an input unit and a second signal path coupled to an output unit; a first filter between the chip pin and the input unit on the first signal path; a second filter between the chip pin and the output unit on the second signal path; a first switch coupling the first signal path to ground; and a second switch coupling the second signal path to ground; wherein the first and second switches are controllable to isolate the input unit from the output unit when the integrated circuit chip is transmitting a radio frequency signal, and to isolate the output unit from the input unit when the integrated circuit chip is receiving a radio frequency signal.
摘要翻译：一种集成电路芯片，包括：芯片引脚，用于引导和关闭芯片上的射频信号; 从芯片引脚分离成耦合到输入单元的第一信号路径和耦合到输出单元的第二信号路径的信号路径; 在所述第一信号路径上的所述芯片引脚和所述输入单元之间的第一滤波器; 芯片引脚和第二信号路径上的输出单元之间的第二滤波器; 将第一信号路径耦合到地的第一开关; 以及将所述第二信号路径耦合到地的第二开关; 其中当所述集成电路芯片正在发送射频信号时，所述第一和第二开关是可控制的，以将所述输入单元与所述输出单元隔离，并且当所述集成电路芯片正在接收射频信号时将所述输出单元与所述输入单元隔离开; 。

18. 发明授权

US09030355B2 Location fix from unknown position 有权
标题翻译：未知位置的位置修复
公开(公告)号：US09030355B2
公开(公告)日：2015-05-12
申请号：US13344098
申请日：2012-01-05
申请人： Murray Robert Jarvis , James Burgess Tidd , Anthony Richard Pratt
发明人： Murray Robert Jarvis , James Burgess Tidd , Anthony Richard Pratt
IPC分类号： G01S19/42 , G01S19/25 , G01S19/24 , G01S19/09
CPC分类号： G01S19/252 , G01S19/09 , G01S19/24
摘要： An apparatus for determining a location of a receiver by using signals received by the receiver from a number of satellites, the apparatus being configured to, when the receiver has been unable to decode a time-of-transmission from the satellite signals, determine a location for the receiver by use of an algorithm that takes an estimate of the location of the receiver as an input, and, when an estimate of the location of the receiver is unavailable, determine an approximate location of the receiver in dependence on the satellite signals and input that approximate location into the algorithm as the estimate of the location of the receiver.
摘要翻译：一种用于通过使用接收机从多个卫星接收的信号来确定接收机的位置的装置，该装置被配置为当接收机不能从卫星信号解码传输时间时，确定位置对于接收机，通过使用将接收机的位置的估计作为输入的算法，并且当接收机的位置的估计不可用时，根据卫星信号确定接收机的大致位置，并且将该近似位置输入到算法中作为接收器位置的估计。

19. 发明授权

US09008240B1 Near maximum likelihood spatial multiplexing receiver 有权
标题翻译：近最大似然空间复用接收机
公开(公告)号：US09008240B1
公开(公告)日：2015-04-14
申请号：US14145799
申请日：2013-12-31
申请人： Cambridge Silicon Radio Limited
发明人： Hong Wan , Fei Tong , Erik Lindskog
IPC分类号： H03D1/00 , H04L27/06 , H04L1/00 , H04B7/04 , H04L27/26
CPC分类号： H04L1/0054 , H04B7/0413 , H04L1/0048 , H04L5/0014 , H04L25/067 , H04L27/22 , H04L27/2649 , H04L27/38 , H04L2025/03426 , H04L2025/03624
摘要： This invention is related to a low-complexity MIMO detector in a wireless communication system with near optimal performance. An initial symbol estimation is performed for a received symbol vector. The soft information of the received symbol vector can be more accurately calculated using every candidate symbol vector of a combined set of candidate symbol vectors, wherein the combined set is generated based on the initial estimation. By combining aspects of both the linear detection and the ML detection, the complexity of the proposed detector becomes orders of magnitude lower than that of a ML detector, but the performance is very close to that of an ML detector.
摘要翻译：本发明涉及具有接近最佳性能的无线通信系统中的低复杂度MIMO检测器。对接收到的符号向量执行初始符号估计。可以使用组合的一组候选符号向量的每个候选符号向量来更精确地计算接收符号向量的软信息，其中基于初始估计生成组合集合。通过组合线性检测和ML检测的方面，提出的检测器的复杂度比ML检测器的复杂度低几个数量级，但性能非常接近于ML检测器。

20. 发明授权

US08989173B2 Increased Bluetooth clock accuracy 有权
标题翻译：提高蓝牙时钟精度
公开(公告)号：US08989173B2
公开(公告)日：2015-03-24
申请号：US12741951
申请日：2008-10-22
申请人： David Richard Hargreaves , Peter Hubball
发明人： Christopher Peter Hubball , David Richard Hargreaves
IPC分类号： H04W56/00 , H04J3/06
CPC分类号： H04W56/002 , H04J3/0664 , H04J3/0697 , H04W4/80
摘要： The present invention provides a communications unit for operation in a communication system in accordance with a protocol that operates to a first clock resolution, the communications unit comprising a first clock, operating to the first resolution, a second clock operating to a second resolution higher than the first resolution, means configured to respond to a request to report a clock value by reporting: (a) the current value of the first clock and (b) information indicating the time on the second clock at which the first clock ticked to its current value.
摘要翻译：本发明提供了一种通信单元，用于根据对第一时钟分辨率进行操作的协议在通信系统中操作，该通信单元包括对第一分辨率进行操作的第一时钟，第二时钟操作为高于第一分辨率，被配置为通过报告来响应要报告时钟值的请求的装置：（a）第一时钟的当前值和（b）指示第一时钟响应其当前时钟的第二时钟上的时间的信息值。

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