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    • 3. 发明申请
    • ON-CHIP TRANSMIT AND RECEIVE FILTERING
    • 片上发送和接收过滤
    • US20150140937A1
    • 2015-05-21
    • US14150145
    • 2014-01-08
    • Cambridge Silicon Radio Limited
    • Michael John StoryTerence Chi-Fung Kwok
    • H04B1/44H04W52/02H04B1/38
    • H04B1/44H04B1/3833H04B1/525H04W52/028Y02D70/00Y02D70/144Y02D70/40
    • An integrated circuit chip including a chip pin configured to direct radio frequency signals on and off chip; a signal path from the chip pin which divides into a first signal path coupled to an input unit and a second signal path coupled to an output unit; a first filter between the chip pin and the input unit on the first signal path; a second filter between the chip pin and the output unit on the second signal path; a first switch coupling the first signal path to ground; and a second switch coupling the second signal path to ground; wherein the first and second switches are controllable to isolate the input unit from the output unit when the integrated circuit chip is transmitting a radio frequency signal, and to isolate the output unit from the input unit when the integrated circuit chip is receiving a radio frequency signal.
    • 一种集成电路芯片,包括:芯片引脚,用于引导和关闭芯片上的射频信号; 从芯片引脚分离成耦合到输入单元的第一信号路径和耦合到输出单元的第二信号路径的信号路径; 在所述第一信号路径上的所述芯片引脚和所述输入单元之间的第一滤波器; 芯片引脚和第二信号路径上的输出单元之间的第二滤波器; 将第一信号路径耦合到地的第一开关; 以及将所述第二信号路径耦合到地的第二开关; 其中当所述集成电路芯片正在发送射频信号时,所述第一和第二开关是可控制的,以将所述输入单元与所述输出单元隔离,并且当所述集成电路芯片正在接收射频信号时将所述输出单元与所述输入单元隔离开; 。
    • 5. 发明申请
    • LOCAL OSCILLATOR FREQUENCY CALIBRATION
    • 本地振荡器频率校准
    • US20150185263A1
    • 2015-07-02
    • US14141021
    • 2013-12-26
    • Cambridge Silicon Radio Limited
    • Timothy Charles ClappDuncan Angus McLeodMichael John Story
    • G01R23/02H03L7/085H03L7/099
    • G01R23/02H03K23/54H03L7/085H03L7/091H03L7/099H03L7/18
    • A frequency locked loop for generating a clock signal, comprising: a controllable oscillator configured to, in dependence on a control signal, generate an oscillator signal having an oscillator signal frequency; a frequency divider coupled to the controllable oscillator configured to reduce the oscillator signal frequency to form a divided oscillator signal frequency; and a frequency detector coupled to the frequency divider and configured to generate the control signal in dependence on a reference signal frequency; wherein the frequency divider comprises a first counter and a second counter, the first counter configured to be clocked by the oscillator signal and to produce a first counter output signal, and the second counter configured to be clocked by the first counter output signal.
    • 一种用于产生时钟信号的锁频环路,包括:可控振荡器,被配置为根据控制信号产生具有振荡器信号频率的振荡器信号; 耦合到所述可控振荡器的分频器,被配置为减小所述振荡器信号频率以形成分频振荡器信号频率; 以及频率检测器,耦合到所述分频器并且被配置为根据参考信号频率产生所述控制信号; 其中所述分频器包括第一计数器和第二计数器,所述第一计数器配置为由所述振荡器信号计时并产生第一计数器输出信号,所述第二计数器被配置为由所述第一计数器输出信号计时。
    • 8. 发明申请
    • INTEGRATED CIRCUIT CHIP INDUCTOR CONFIGURATION
    • 集成电路芯片电感器配置
    • US20150200052A1
    • 2015-07-16
    • US14151943
    • 2014-01-10
    • Cambridge Silicon Radio Limited
    • Michael John Story
    • H01F30/12H04B1/04H01F27/34
    • H04B1/04H01F17/0006H01F27/346
    • An integrated circuit chip including a first inductor; a second inductor having n1 turns and located a distance r1 from the first inductor; and a third inductor having n2 turns and located a distance r2 from the first inductor; wherein the second and third inductors are coupled so as to cause current to circulate around the second inductor in a first rotational direction and around the third inductor in a second rotational direction opposite to the first rotational direction; and wherein n1, n2, r1 and r2 are such that current induced in the first inductor due to magnetic coupling from the second inductor is negated by current induced in the first inductor due to magnetic coupling from the third inductor.
    • 一种集成电路芯片,包括第一电感器; 具有n1圈的第二电感器并且与第一电感器的距离r1定位; 以及第三电感器,其具有n2个匝并且与所述第一电感器定位距离r2; 其中所述第二和第三电感器被耦合以使得电流在与所述第一旋转方向相反的第二旋转方向上沿第一旋转方向围绕所述第二电感器循环并围绕所述第三电感器循环; 并且其中n1,n2,r1和r2使得由于来自第二电感器的磁耦合而在第一电感器中感应的电流由于由第三电感器的磁耦合而在第一电感器中感应的电流而被否定。