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11. 发明授权

US08704569B2 Delay locked loop circuit and method 有权
标题翻译：延时锁相环电路及方法
公开(公告)号：US08704569B2
公开(公告)日：2014-04-22
申请号：US13718783
申请日：2012-12-18
申请人： MOSAID Technologies Incorporated
发明人： Dieter Haerle , Tony Mai , Peter Vlasenko
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L7/0812 , H03L7/0891 , H03L7/0895 , H03L7/095 , H03L7/10
摘要： A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.
摘要翻译：延迟锁定环包括初始化电路，其确保将DLL初始化为不接近延迟与控制电压特性的任一端的工作点。初始化电路强制DLL最初从初始延迟开始搜索锁定点，延迟在一个方向上变化，迫使DLL跳过第一个锁定点。初始化电路仅允许DLL改变从初始延迟到达到工作点的一个方向的电压控制延迟环的延迟。

12. 发明申请

US20140105113A1 Network Architecture for Data Communication 有权
标题翻译：数据通信网络架构
公开(公告)号：US20140105113A1
公开(公告)日：2014-04-17
申请号：US14135167
申请日：2013-12-19
申请人： MOSAID Technologies Incorporated
发明人： Antonio Francescon , Davide Mandato
IPC分类号： H04W24/02 , H04W88/06
CPC分类号： G05F1/66 , H04W24/00 , H04W24/02 , H04W24/04 , H04W88/06 , H04W88/08
摘要： This invention relates to a network architecture for data communication between data sources and data destinations via network nodes and at least one data concentrator. According to the invention the nodes (2, 4) are conceived to communicate with a data concentrator (1) in both directions either via a permanently operative network (8) in the multihop mode or via an occasionally operative network (5) in wireless connection with mobile user nodes (6) in the nomadic mode. Means for commutation are provided to detect faulty multihop nodes and to activate nomadic nodes instead until the fault disappears, in order to maintain the overall functionality of the network. Moreover the network according to the invention allows to share the data collected by mobile users with other mobile users, thus forming a peer-to-peer network.
摘要翻译：本发明涉及用于经由网络节点和至少一个数据集中器的数据源和数据目的地之间的数据通信的网络架构。根据本发明，节点（2,4）被设想为在多重模式下经由永久操作的网络（8）或经由无线连接中的偶尔操作的网络（5）在两个方向上与数据集中器（1）进行通信移动用户节点（6）处于游牧模式。提供换向的手段来检测故障多跳节点并激活游牧节点，直到故障消失为止，以维持网络的整体功能。此外，根据本发明的网络允许与其他移动用户共享移动用户收集的数据，从而形成对等网络。

13. 发明授权

US08694692B2 Apparatus and method for producing device identifiers for serially interconnected devices of mixed type 有权
标题翻译：用于生产混合型串联互连设备的设备标识符的设备和方法
公开(公告)号：US08694692B2
公开(公告)日：2014-04-08
申请号：US13671248
申请日：2012-11-07
申请人： Mosaid Technologies Incorporated
发明人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
IPC分类号： G06F3/00
CPC分类号： G06F13/4243
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.
摘要翻译：多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。每个设备都有其设备类型的设备类型信息。作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包括在设备中的计算器执行计算以生成伴随用于另一设备的馈送DT的ID，并且将馈送的ID锁存在设备的寄存器中。在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。根据设备类型匹配确定，DT与所生成或接收的ID组合。组合的DT和ID作为传送到下一个设备的分组。在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。参考提供给互连设备的设备类型，依次生成ID。将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。

14. 发明申请

US20140093057A1 OUTLET ADD-ON MODULE 审中-公开
标题翻译： OUTLET ADD-ON模块
公开(公告)号：US20140093057A1
公开(公告)日：2014-04-03
申请号：US14057724
申请日：2013-10-18
申请人： MOSAID Technologies Incorporated
发明人： Ami HAZANI , Shlomo BUTBUL , Rafael Gil KOBY , Yehuda BINDER
IPC分类号： H04B3/54
CPC分类号： H04B3/542 , H01R13/719 , H01R31/065 , H04B2203/5408
摘要： A method and an apparatus for upgrading an existing service outlet (e.g. LAN, telephone, power or CATV outlet) in a house by adding functionality thereto. The functionality is added by an add-on module, connected electrically and secured mechanically to the existing outlet. Several attachment devices are exampled, including surface attachment, side clamping, snap locking, strap securing and fastening screws. The add-on module may include a service connector for retaining the basic existing outlet function. The module may be attached in a permanent way or by using a detachable solution.
摘要翻译：一种用于通过向其添加功能来升级房屋中的现有服务插座（例如LAN，电话，电源或CATV插座）的方法和装置。该功能由附加模块添加，电连接并机械地连接到现有插座。示例中包括几个附件，包括表面附件，侧面夹紧，卡扣锁定，皮带固定和紧固螺丝。附加模块可以包括用于保持基本现有插座功能的服务连接器。模块可以以永久的方式连接或通过使用可拆卸的解决方案。

15. 发明申请

US20140092891A1 SYSTEM AND METHOD PROVIDING INTEROPERABILITY BETWEEN CELLULAR AND OTHER WIRELESS SYSTEMS 审中-公开
标题翻译：提供细胞与其他无线系统之间的互操作性的系统和方法
公开(公告)号：US20140092891A1
公开(公告)日：2014-04-03
申请号：US14097506
申请日：2013-12-05
申请人： MOSAID Technologies Incorporated
发明人： Nima Ahmadvand , Hanwu Hu
IPC分类号： H04W88/10
CPC分类号： H04W88/10 , H04M15/00 , H04M17/00 , H04M17/02 , H04W4/24 , H04W12/08 , H04W36/0066 , H04W48/18 , H04W74/004 , H04W84/042 , H04W84/12 , H04W88/06 , H04W92/02
摘要： A method and corresponding apparatus for providing a cellular subscriber with access to a WLAN are provided. They involve identifying a multimode mobile terminal, which corresponds to the subscriber and the WLAN from an access request. Based on the identification, the WLAN is authorized to provide the mobile terminal with access. The mobile terminal is then provided with access to the WLAN as a cellular subscriber and enables interoperability between the two networks. For example, the subscriber does not have to supply a credit card to pay for WLAN access directly. Instead, the subscriber pays a cellular network provider, and, in turn, the cellular network provider pays a WLAN provider for the access.
摘要翻译：提供了一种用于向蜂窝用户提供对WLAN的接入的方法和相应的装置。它们涉及从访问请求中识别对应于用户和WLAN的多模移动终端。基于识别，WLAN被授权向移动终端提供接入。然后移动终端作为蜂窝用户提供对WLAN的接入，并实现两个网络之间的互操作性。例如，用户不必提供信用卡来直接支付WLAN访问费用。相反，用户支付蜂窝网络提供商，而蜂窝网络提供商又向WLAN提供商支付接入。

16. 发明申请

US20140084977A1 Wide Frequency Range Delay Locked Loop 审中-公开
标题翻译：宽频率范围延迟锁定环
公开(公告)号：US20140084977A1
公开(公告)日：2014-03-27
申请号：US14092788
申请日：2013-11-27
申请人： MOSAID Technologies Incorporated
发明人： Peter Vlasenko , Dieter Haerle
IPC分类号： H03L7/10
CPC分类号： H03L7/081 , H03L7/0814 , H03L7/0818 , H03L7/0891 , H03L7/095 , H03L7/10
摘要： A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.
摘要翻译：延迟锁定环路在宽频率范围内工作，具有高精度，小面积使用，低功耗和短锁定时间。该DLL结合了模拟域和数字域。数字域负责初始锁定和操作点稳定性，并在达到锁定后冻结。模拟域在达到锁定后负责正常运行，并使用较小的硅面积和低功耗提供高精度。

17. 发明授权

US08675408B2 Non-volatile memory device having configurable page size 有权
标题翻译：具有可配置页面大小的非易失性存储器件
公开(公告)号：US08675408B2
公开(公告)日：2014-03-18
申请号：US13743899
申请日：2013-01-17
申请人： MOSAID Technologies Incorporated
发明人： Jin-Ki Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10 , G11C15/046 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26
摘要： A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.
摘要翻译：具有至少一个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小。每个存储体包括至少两个具有对应页面缓冲器的存储器平面，其中响应于配置数据和地址数据，同时选择性地访问存储器层的任何数量和组合。在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。通过选择性地调整存储体的页面大小，相应地调整块大小。

18. 发明申请

US20140071781A1 VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY 审中-公开
标题翻译：低压转换器用于高速存储器
公开(公告)号：US20140071781A1
公开(公告)日：2014-03-13
申请号：US14080302
申请日：2013-11-14
申请人： MOSAID Technologies Incorporated
发明人： Hong Beom PYEON , Bruce MILLAR
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C7/20 , G11C11/4072 , G11C11/4074
摘要： A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.
摘要翻译：适用于高速存储器件的降压转换器（VDC）。 VDC包括一个稳定的驱动器和有源驱动器以及至少一个额外的晶体管。稳定的驱动器和有源驱动器在器件启动期间由晶体管开关耦合，以提供对工作电压和电流的快速上升。启动后，稳定的驱动器和主动驱动功能保持稳定的工作电压和电流。在发出表示存储器的读取，写入和/或刷新的活动命令时，附加晶体管被数字控制以驱动工作电压和电流。以这种方式，附加晶体管对存储器阵列中的活动引起的工作电压和电流的波动提供快速补偿。

19. 发明申请

US20140029347A1 MEMORY SYSTEM HAVING A PLURALITY OF SERIALLY CONNECTED DEVICES 有权
标题翻译：具有多个连续连接器件的存储器系统
公开(公告)号：US20140029347A1
公开(公告)日：2014-01-30
申请号：US14045857
申请日：2013-10-04
申请人： MOSAID Technologies Incorporated
发明人： HakJune Oh
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G11C7/10 , G11C7/22 , G11C8/12 , G11C16/08 , G11C16/32
摘要： A semiconductor memory device and system are disclosed. The memory device includes a memory, a plurality of inputs, and a device identification register for storing register bits that distinguish the memory device from other possible memory devices. Circuitry for comparing identification bits in the information signal with the register bits provides positive or negative indication as to whether the identification bits match the register bits. If the indication is positive, then the memory device is configured to respond as having been selected by a controller. If the indication is negative, then the memory device is configured to respond as having not been selected by the controller. A plurality of outputs release a set of output signals towards a next device.
摘要翻译：公开了一种半导体存储器件和系统。存储器件包括存储器，多个输入端和用于存储将存储器件与其它可能存储器件区分开的寄存器位的器件识别寄存器。用于将信息信号中的标识位与寄存器位进行比较的电路提供关于标识位是否匹配寄存器位的正或负指示。如果指示为正，则存储器设备被配置为响应为由控制器选择。如果指示为负，则存储器设备被配置为响应为未被控制器选择。多个输出向一个下一个设备释放一组输出信号。

20. 发明授权

US08639912B2 Method and system for packet processing 有权
标题翻译：分组处理方法和系统
公开(公告)号：US08639912B2
公开(公告)日：2014-01-28
申请号：US12619355
申请日：2009-11-16
申请人： Arthur John Low , Stephen J. Davis
发明人： Arthur John Low , Stephen J. Davis
IPC分类号： G06F15/00 , G06F3/00
CPC分类号： H04L67/42 , H04L49/90 , H04L49/9036 , H04L63/0428 , H04L63/0485 , H04L67/34 , H04L69/22 , H04L69/329
摘要： A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyze the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is no next process for a packet at which time it is provided to an output port.
摘要翻译：公开了一种用于处理数据的数据处理器和方法。处理器具有用于接收待处理数据的数据包的输入端口。主控制器用于分析分组并提供包括要在数据分组上执行的进程列表及其排序的报头。主控制器被编程有与处理器的整体处理功能相关的过程相关数据。标题附加到数据包。具有附加标题信息的分组被存储在缓冲器中。缓冲器控制器用于基于分组内的报头来确定存储在缓冲器内的每个分组，以处理分组的下一个处理器。然后，控制器将该分组提供给所确定的处理器进行处理。返回处理后的数据包，表示处理完成。例如，可以从进程列表中删除该进程。缓冲器控制器重复地进行下一个处理的确定，直到在其被提供给输出端口的分组没有下一个处理为止。

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