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11. 发明授权

US09391271B1 Resistive random access memory and manufacturing method thereof 有权
标题翻译：电阻随机存取存储器及其制造方法
公开(公告)号：US09391271B1
公开(公告)日：2016-07-12
申请号：US14670429
申请日：2015-03-27
申请人： Powerchip Technology Corporation
发明人： Mao-Teng Hsu , Chiu-Tsung Huang
IPC分类号： H01L29/80 , H01L21/00 , H01L21/337 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1226 , H01L27/2436 , H01L27/2481 , H01L45/1616 , H01L45/1683
摘要： A resistive random access memory including a substrate, a dielectric layer, and at least one memory cell string is provided. The dielectric layer is disposed on the substrate. The memory cell string includes memory cells and at least one first interconnect structure. The memory cells are vertically and adjacently disposed in the dielectric layer, and each memory cells includes a first conductive line, a second conductive line, and a variable resistance structure. The second conductive line is disposed at one side of the first conductive line, and the top surface of the second conductive line is higher than the top surface of the first conductive line. The variable resistance structure is disposed between the first conductive line and the second conductive line. The variable resistance structures in the vertically adjacent memory cells are isolated from each other. The first interconnect structure is connected to the vertically adjacent first conductive lines.
摘要翻译：提供了包括基板，电介质层和至少一个存储单元串的电阻随机存取存储器。电介质层设置在基板上。存储单元串包括存储单元和至少一个第一互连结构。存储单元垂直并相邻地布置在电介质层中，并且每个存储单元包括第一导电线，第二导线和可变电阻结构。第二导线设置在第一导线的一侧，第二导线的顶表面高于第一导线的顶表面。可变电阻结构设置在第一导线与第二导线之间。垂直相邻的存储单元中的可变电阻结构彼此隔离。第一互连结构连接到垂直相邻的第一导电线。

12. 发明授权

US09171935B2 FinFET formation with late fin reveal 有权
标题翻译： FinFET形成与晚期翅膀显露
公开(公告)号：US09171935B2
公开(公告)日：2015-10-27
申请号：US14200104
申请日：2014-03-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Seong-Dong Kim , Myung-Hee Na , Jin Z. Wallner , Thomas A. Wallner , Qintao Zhang
IPC分类号： H01L21/337 , H01L21/8234 , H01L29/66
CPC分类号： H01L29/66795 , H01L29/66545
摘要： A FinFET semiconductor device fabrication process includes forming a plurality of FinFET fins upon a semiconductor substrate, forming a first dielectric layer upon the semiconductor substrate so that an upper surface of the first dielectric layer is coplanar with upper surfaces of the FinFET fins, forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins, revealing the FinFET fins by removing first portions of the first dielectric layer from source-drain regions, removing the dummy gates, and subsequent to the removal of the dummy gates, revealing the FinFET fins by removing second portions of the first dielectric layer from channel regions.
摘要翻译： FinFET半导体器件制造工艺包括在半导体衬底上形成多个FinFET鳍，在半导体衬底上形成第一电介质层，使得第一电介质层的上表面与FinFET鳍的上表面共面，形成多个在FinFET翅片和与FinFET翅片正交的第一介质层之间的虚拟栅极，通过从源极 - 漏极区域去除第一介电层的第一部分，去除虚拟栅极，并且在去除虚拟栅极之后，露出FinFET鳍片门，通过从沟道区域去除第一介电层的第二部分而露出FinFET鳍片。

13. 发明授权

US09059307B1 Method of implementing buried FET below and beside FinFET on bulk substrate 有权
标题翻译：在散装衬底上实现FinFET下方和FinFET旁边的方法
公开(公告)号：US09059307B1
公开(公告)日：2015-06-16
申请号：US14289594
申请日：2014-05-28
申请人： International Business Machines Corporation
发明人： Karl R. Erickson , Phil C. Paone , David P. Paulsen , John E. Sheets, II , Gregory J. Uhlmann , Kelly L. Williams
IPC分类号： H01L21/336 , H01L21/00 , H01L21/84 , H01L21/337 , H01L21/8234 , H01L29/66
CPC分类号： H01L27/0886 , G06F17/5045 , G06F17/5068 , H01L21/26586 , H01L21/30604 , H01L21/324 , H01L21/823418 , H01L21/823431 , H01L23/49838 , H01L27/088 , H01L29/41775 , H01L29/41791 , H01L29/4232 , H01L29/66553 , H01L29/66803 , H01L29/78 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： A method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with added device drive strength with buried field effect transistors (FETs) below and beside a traditional FinFET on a bulk substrate, and a design structure on which the subject circuit resides are provided. Buried field effect transistors (FETs) are formed on either side and under the traditional FinFET. The gate of the FinFET becomes the gate of the parallel buried (FETs) and allows self alignment to the underlying sources and drains of the buried FET devices in the bulk semiconductor.
摘要翻译：一种用于实现增强的晶体管拓扑的方法和电路，其使得能够通过附加的器件驱动强度增加电流能力，并且在散装衬底上的传统FinFET下方和旁边的掩埋场效应晶体管（FET）以及设置有被摄体电路的设计结构。埋地场效应晶体管（FET）形成在传统FinFET的两侧和下方。 FinFET的栅极成为并行掩埋（FET）的栅极，并允许自身对准散装半导体中的掩埋FET器件的底层源极和漏极。

14. 发明授权

US09059206B2 Epitaxial grown extremely shallow extension region 有权
标题翻译：外延生长非常浅的延伸区域
公开(公告)号：US09059206B2
公开(公告)日：2015-06-16
申请号：US13709095
申请日：2012-12-10
申请人： International Business Machines Corporation
发明人： Bruce B. Doris , Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/337 , H01L21/336 , H01L29/66 , H01L29/78 , H01L29/165
CPC分类号： H01L29/6653 , H01L29/165 , H01L29/66545 , H01L29/66553 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A method to scale a MOSFET structure while maintaining gate control is disclosed. The extension regions of the MOSFET are formed by epitaxial growth and can be formed after the completion of high temperature processing. The extensions can be extremely shallow and have an abrupt interface with the channel. A dummy gate can establish the position of the abrupt interfaces and thereby define the channel length. The gate electrode can be formed to align perfectly with the channel, or to overlap the extension tip.
摘要翻译：公开了一种在保持栅极控制的同时缩小MOSFET结构的方法。 MOSFET的延伸区域通过外延生长形成，并且可以在高温处理完成之后形成。扩展可以非常浅，并且与通道具有突然的接口。虚拟门可以建立突然接口的位置，从而定义通道长度。栅电极可以形成为与通道完美对准，或与延伸尖重叠。

15. 发明授权

US08963219B2 Tunnel field effect transistor 有权
标题翻译：隧道场效应晶体管
公开(公告)号：US08963219B2
公开(公告)日：2015-02-24
申请号：US13270898
申请日：2011-10-11
申请人： Gilberto Curatola , Dusan Golubovic , Johannes Josephus Theodorus Marinus Donkers , Guillaume Boccardi , Hans Mertens
发明人： Gilberto Curatola , Dusan Golubovic , Johannes Josephus Theodorus Marinus Donkers , Guillaume Boccardi , Hans Mertens
IPC分类号： H01L29/66 , H01L29/76 , H01L21/337 , H01L29/739 , B82Y10/00 , H01L29/10 , H01L29/165
CPC分类号： H01L29/7391 , B82Y10/00 , H01L29/1033 , H01L29/165 , H01L29/66356 , H01L29/7613
摘要： A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.
摘要翻译：隧道场效应晶体管及其制造方法。晶体管包括半导体衬底。晶体管还包括位于衬底的主表面上的栅极。晶体管还包括第一导电类型的漏极。晶体管还包括在栅极下延伸的第二导电类型的源。源极通过沟道区和栅极电介质与栅极分离。晶体管可操作以允许电荷载流子从反型层通过源的上表面穿透。

16. 发明授权

US08921173B2 Deep silicon via as a drain sinker in integrated vertical DMOS transistor 有权
标题翻译：深硅通孔作为集成垂直DMOS晶体管的漏极沉降片
公开(公告)号：US08921173B2
公开(公告)日：2014-12-30
申请号：US13484238
申请日：2012-05-30
申请人： Sharon Levin , Zachary K. Lee , Shye Shapira
发明人： Sharon Levin , Zachary K. Lee , Shye Shapira
IPC分类号： H01L21/337
CPC分类号： H01L29/7809 , H01L21/823487 , H01L21/82385 , H01L21/823857 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/41741 , H01L29/4916
摘要： A vertical DMOS device implements one or more deep silicon via (DSV) plugs, thereby significantly reducing the layout area and on-resistance (RDSON) of the device. The DSV plugs extend through a semiconductor substrate to contact a conductively doped buried diffusion region, which forms the drain of the vertical DMOS device. Methods for fabricating the vertical DMOS device are compatible with conventional sub-micron VLSI processes, such that the vertical DMOS device can be readily fabricated on the same integrated circuit as CMOS devices and analog devices, such as lateral double-diffused MOS (LDMOS) devices.
摘要翻译：垂直DMOS器件实现了一个或多个深硅通孔（DSV）插头，从而显着减少了器件的布局面积和导通电阻（RDSON）。 DSV插头延伸穿过半导体衬底以接触形成垂直DMOS器件的漏极的导电掺杂掩埋扩散区域。用于制造垂直DMOS器件的方法与传统的亚微米VLSI工艺兼容，使得垂直DMOS器件可以容易地制造在与CMOS器件和模拟器件相同的集成电路上，例如横向双扩散MOS（LDMOS）器件。

17. 发明授权

US08901533B2 Semiconductor devices and methods of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08901533B2
公开(公告)日：2014-12-02
申请号：US13789873
申请日：2013-03-08
申请人： Samsung Electronics Co., Ltd.
发明人： Sang-moon Lee , Young-jin Cho
IPC分类号： H01L29/12 , H01L31/0336 , H01L31/072 , H01L21/00 , H01L21/337 , H01L29/778 , H01L29/10 , H01L29/15 , H01L29/66 , H01L29/51 , H01L29/06
CPC分类号： H01L29/78 , H01L29/0657 , H01L29/1075 , H01L29/1079 , H01L29/15 , H01L29/205 , H01L29/517 , H01L29/66462 , H01L29/7781 , H01L29/7783
摘要： Semiconductor devices including a substrate (e.g., silicon substrate), a multi-layer structure disposed on a portion of the substrate, and at least one electrode disposed on the multi-layer structure and methods of manufacturing the same are provided. The multi-layer structure may include an active layer containing a Group III-V material and a current blocking layer disposed between the substrate and the active layer. The semiconductor device may further include a buffer layer disposed between the substrate and the active layer. In a case that the substrate is a p-type, the buffer layer may be an n-type material layer and the current blocking layer may be a p-type material layer. The current blocking layer may contain a Group III-V material. A mask layer having an opening may be disposed on the substrate so that the multi-layer structure may be disposed on the portion of the substrate exposed by the opening.
摘要翻译：提供了包括衬底（例如，硅衬底），设置在衬底的一部分上的多层结构以及设置在多层结构上的至少一个电极的半导体器件及其制造方法。多层结构可以包括含有III-V族材料的有源层和设置在衬底和有源层之间的电流阻挡层。半导体器件还可以包括设置在衬底和有源层之间的缓冲层。在基板是p型的情况下，缓冲层可以是n型材料层，电流阻挡层可以是p型材料层。电流阻挡层可以含有III-V族材料。具有开口的掩模层可以设置在基板上，使得多层结构可以设置在由开口暴露的基板的部分上。

18. 发明授权

US08859354B2 Transistors and fabrication method thereof 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US08859354B2
公开(公告)日：2014-10-14
申请号：US13831995
申请日：2013-03-15
申请人： Semiconductor Manufacturing International Corp.
发明人： Deyuan Xiao
IPC分类号： H01L21/338 , H01L21/337 , H01L29/06 , H01L29/732 , H01L29/66 , H01L29/778
CPC分类号： H01L29/66462 , H01L21/8252 , H01L27/088 , H01L29/0847 , H01L29/2003 , H01L29/517 , H01L29/7783
摘要： A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a quantum well layer on the semiconductor substrate. The method also includes forming a potential energy barrier layer on the semiconductor substrate, and forming an isolation structure to isolate different transistor regions. Further, the method includes patterning the transistor region to form trenches by removing portions of the quantum well layer and the potential energy barrier layer corresponding to a source region and a drain region, and filling trenches with a semiconductor material to form a source and a drain. Further, the method also includes forming a gate structure on a portion of the quantum well layer and the potential energy barrier layer corresponding to a gate region.
摘要翻译：提供了一种用于制造晶体管的方法。该方法包括提供半导体衬底，并在半导体衬底上形成量子阱层。该方法还包括在半导体衬底上形成势能阻挡层，并形成隔离结构以隔离不同的晶体管区域。此外，该方法包括通过去除与源极区和漏极区相对应的量子阱层和势能势垒层的部分来形成晶体管形成沟槽，并且用半导体材料填充沟槽以形成源极和漏极。此外，该方法还包括在量子阱层的一部分上形成栅极结构和对应于栅极区的势垒层。

19. 发明授权

US08846465B2 Integrated circuit with multi recessed shallow trench isolation 有权
标题翻译：集成电路具有多凹槽浅沟槽隔离
公开(公告)号：US08846465B2
公开(公告)日：2014-09-30
申请号：US13910757
申请日：2013-06-05
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Lin Lee , Chang-Yun Chang
IPC分类号： H01L21/337 , H01L21/762
CPC分类号： H01L21/762 , H01L21/76232
摘要： A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.
摘要翻译：提供了一种用于在集成电路的衬底上形成多凹槽浅沟槽隔离结构的系统和方法。集成电路包括衬底，在衬底中形成的至少两个浅沟槽隔离（STI）结构，设置在至少两个STI结构中的氧化物填充物，以及设置在至少两个STI结构中的氧化物填充物上的半导体器件。第一STI结构形成为第一深度，并且第二STI结构形成为第二深度。氧化物填充物填充至少两个STI结构，并且第一深度和第二深度基于设置在其上的半导体器件的半导体器件特性。

20. 发明授权

US08759171B2 Field controlled diode with positively biased gate 有权
标题翻译：具有正偏置栅极的场控二极管
公开(公告)号：US08759171B2
公开(公告)日：2014-06-24
申请号：US14099975
申请日：2013-12-08
申请人： Texas Instruments Incorporated
发明人： Akram A. Salman
IPC分类号： H01L21/337
CPC分类号： H01L29/66356 , H01L27/0255 , H01L27/0629 , H01L29/66893 , H01L29/7391 , H01L29/7392 , H01L29/808
摘要： An integrated circuit containing a field controlled diode which includes a p-type channel region between an upper gate and a lower n-type depletion gate, a p-type anode in a p-type anode well abutting the channel region, and an n-type cathode in a p-type anode well abutting the channel region opposite from the anode well. An n-type lower gate link connects the lower gate to the surface of the substrate. A surface control element is located at the surface of the channel region between the cathode and the upper gate. A process of forming the integrated circuit containing the field controlled diode is described.
摘要翻译：包含场控二极管的集成电路，其包括上栅极和下n型耗尽栅之间的p型沟道区，邻接沟道区的p型阳极中的p型阳极，在与阳极阱相对的沟道区域邻接的p型阳极阱中形成阴极。 n型下栅极链路将下栅极连接到衬底的表面。表面控制元件位于阴极和上栅极之间的沟道区域的表面。描述形成包含场控二极管的集成电路的过程。

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