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11. 发明授权

US09059710B2 Systems, circuits, devices, and methods with bidirectional bipolar transistors 有权
公开(公告)号：US09059710B2
公开(公告)日：2015-06-16
申请号：US14514988
申请日：2014-10-15
申请人： Ideal Power, Inc.
发明人： Richard A. Blanchard , William C. Alexander
IPC分类号： H01L29/86 , H03K17/66 , H02M3/158 , H01L29/739 , H01L29/08 , H01L29/16 , H01L29/737 , H02M1/088 , H02M7/797 , H03K3/012 , H03K17/687 , H01L29/06 , H01L29/10
CPC分类号： H02M3/158 , H01L27/0755 , H01L27/0823 , H01L27/0828 , H01L29/0619 , H01L29/0649 , H01L29/0804 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/16 , H01L29/1604 , H01L29/41708 , H01L29/42304 , H01L29/73 , H01L29/732 , H01L29/7375 , H01L29/7393 , H01L29/7395 , H02M1/088 , H02M3/1582 , H02M7/797 , H02M11/00 , H03K3/012 , H03K17/60 , H03K17/66 , H03K17/687
摘要： Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.

12. 发明申请

US20140264738A1 FOLDED CONICAL INDUCTOR 有权
标题翻译：折叠式电感器
公开(公告)号：US20140264738A1
公开(公告)日：2014-09-18
申请号：US14294485
申请日：2014-06-03
申请人： International Business Machines Corporation
发明人： Robert L. Barry , Robert A. Groves , Venkata N.R. Vanukuru
IPC分类号： H01L29/86
CPC分类号： H01L29/86 , H01F17/0013 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor inductor structure may include a first spiral structure, located on a first metal layer, having a first outer-spiral electrically conductive track and a first inner-spiral electrically conductive track separated from the first outer-spiral electrically conductive track by a first dielectric material. A second spiral structure, located on a second metal layer, having a second outer-spiral electrically conductive track and a second inner-spiral electrically conductive track separated from the second outer-spiral electrically conductive track by a second dielectric material may also be provided. The first outer-spiral electrically conductive track may be electrically coupled to the second outer-spiral electrically conductive track and the first inner-spiral electrically conductive track may be electrically coupled to the second inner-spiral electrically conductive track. The first outer-spiral conductive track is laterally offset relative to the second outer-spiral conductive track and the first inner-spiral conductive track is laterally offset relative to the second inner-spiral conductive track.
摘要翻译：半导体电感器结构可以包括位于第一金属层上的第一螺旋结构，其具有第一外螺旋导电轨道和通过第一电介质与第一外螺旋导电轨道分开的第一内螺旋导电轨道材料。还可以提供位于第二金属层上的第二螺旋结构，其具有第二外螺旋导电轨道和通过第二介电材料与第二外螺旋导电轨道分离的第二内螺旋导电轨道。第一外螺旋导电轨道可以电耦合到第二外螺旋导电轨道，并且第一内螺旋导电轨道可以电耦合到第二内螺旋导电轨道。第一外螺旋导电轨道相对于第二外螺旋导电轨道横向偏移，并且第一内螺旋导电轨道相对于第二内螺旋导电轨道横向偏移。

13. 发明授权

US08754498B2 Antifuse and method of making the antifuse 有权
标题翻译：防腐剂及其制造方法
公开(公告)号：US08754498B2
公开(公告)日：2014-06-17
申请号：US12606497
申请日：2009-10-27
申请人： Yue-Der Chih , Chrong Jung Lin
发明人： Yue-Der Chih , Chrong Jung Lin
IPC分类号： H01L29/86
CPC分类号： H01L23/5252 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse.
摘要翻译：制造反熔丝的方法包括提供具有位线扩散区域和电容器扩散区域的衬底。栅极电介质层形成在衬底上，并且在栅极电介质层上形成字线。在形成栅极电介质层的分离工艺步骤中，在电容器扩散区上形成氧化物层。在上方形成选择线接触并与氧化物层接触以形成具有作为电容器的电容器电介质层的氧化物层的电容器。选择线触点被配置为施加电压以导致氧化物层的永久性击穿来编程反熔丝。

14. 发明授权

US08742539B2 Semiconductor component and method for producing a semiconductor component 有权
标题翻译：半导体元件的制造方法及半导体元件的制造方法
公开(公告)号：US08742539B2
公开(公告)日：2014-06-03
申请号：US13560626
申请日：2012-07-27
申请人： Joachim Weyers , Kevni Bueyuektas , Franz Hirler , Anton Mauder
发明人： Joachim Weyers , Kevni Bueyuektas , Franz Hirler , Anton Mauder
IPC分类号： H01L29/86
CPC分类号： H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the invention relates to a semiconductor component with a semiconductor body with a top side and with a bottom side. A first coil that is monolithically integrated with the semiconductor body is arranged distant from the bottom side and comprises N first windings, wherein N≧1. The first coil has a first coil axis that extends in a direction different from a surface normal of the bottom side.
摘要翻译：本发明的一个方面涉及具有顶侧和底侧的半导体本体的半导体部件。与半导体本体整体地集成的第一线圈布置成远离底侧，并且包括N个第一绕组，其中N≥1。第一线圈具有沿与底侧的表面法线不同的方向延伸的第一线圈轴线。

15. 发明授权

US08569861B2 Vertically integrated systems 有权
公开(公告)号：US08569861B2
公开(公告)日：2013-10-29
申请号：US12975847
申请日：2010-12-22
申请人： Alan O'Donnell , Santiago Iriarte , Mark J. Murphy , Colin Lyden , Gary Casey , Eoin Edward English
发明人： Alan O'Donnell , Santiago Iriarte , Mark J. Murphy , Colin Lyden , Gary Casey , Eoin Edward English
IPC分类号： H01L29/86 , H01L29/8605
CPC分类号： G01N27/226 , B81B7/00 , B81B7/007 , B81B2201/0214 , G01N27/26 , G01N27/4148 , H01F17/00 , H01F17/04 , H01L21/82 , H01L23/3677 , H01L23/38 , H01L23/473 , H01L23/481 , H01L23/58 , H01L24/05 , H01L24/13 , H01L24/48 , H01L24/94 , H01L25/16 , H01L25/167 , H01L27/0694 , H01L27/14 , H01L27/15 , H01L28/00 , H01L28/10 , H01L28/20 , H01L28/60 , H01L28/82 , H01L28/86 , H01L28/90 , H01L31/0392 , H01L31/0525 , H01L31/0547 , H01L31/056 , H01L31/06 , H01L35/00 , H01L35/28 , H01L35/30 , H01L2224/04042 , H01L2224/05554 , H01L2224/0556 , H01L2224/0557 , H01L2224/32145 , H01L2224/48091 , H01L2224/48265 , H01L2225/06531 , H01L2924/00014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/1461 , H01L2924/15787 , H01L2924/15788 , H01L2924/16195 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H02S10/10 , H02S40/38 , Y02E10/50 , Y02E10/52 , H01L2924/00 , H01L2224/45099 , H01L2224/05552 , H01L2224/85399 , H01L2224/05599
摘要： Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

16. 发明授权

US08470683B2 Method and electronic device for a simplified integration of high precision thinfilm resistors 有权
标题翻译：方法和电子设备，用于简化高精度薄膜电阻的集成
公开(公告)号：US08470683B2
公开(公告)日：2013-06-25
申请号：US13032426
申请日：2011-02-22
申请人： Christoph Dirnecker , Wolfgang Ploss
发明人： Christoph Dirnecker , Wolfgang Ploss
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： H01L28/20 , H01L21/76816 , H01L23/5228 , H01L27/016 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR.
摘要翻译：本发明涉及一种制造集成电路的方法。沉积用作薄膜电阻器（TFR）的材料的电阻层。第一电绝缘层沉积在TFR的电阻层上。沉积导电材料的导电层。没有导电层而没有区域与TFR的电阻层重叠。第二电绝缘层沉积在导电层的顶部上。通过第二绝缘层蚀刻第一VIA开口，没有导电层的区域与导电层相邻并且通过第一绝缘层直到TFR的电阻层。在第一VIA开口中沉积导电材料，以电连接TFR的导电层和电阻层。

17. 发明授权

US08466536B2 Shield-modulated tunable inductor device 有权
标题翻译：屏蔽调制可调电感器件
公开(公告)号：US08466536B2
公开(公告)日：2013-06-18
申请号：US12904812
申请日：2010-10-14
申请人： Alvin Leng Sun Loke , Tin Tin Wee
发明人： Alvin Leng Sun Loke , Tin Tin Wee
IPC分类号： H01L27/08 , H01L29/86
CPC分类号： H01L27/0617 , H01L23/5225 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is presented here. The semiconductor device includes an integrated inductor formed on a semiconductor substrate, a transistor arrangement formed on the semiconductor substrate to modulate loop current induced by the integrated inductor, dielectric material to insulate the integrated inductor from the transistor arrangement, and a controller coupled to the transistor arrangement. The controller is used to select conductive and nonconductive operating states of the transistor arrangement. A conductive operating state of the transistor arrangement allows formation of induced loop current in the transistor arrangement, and a nonconductive operating state of the transistor arrangement inhibits formation of induced loop current in the transistor arrangement.
摘要翻译：这里介绍一种半导体器件。半导体器件包括形成在半导体衬底上的集成电感器，形成在半导体衬底上的晶体管装置，用于调制由集成电感器引起的环路电流，将集成电感器与晶体管装置绝缘的绝缘材料以及耦合到晶体管的控制器安排。控制器用于选择晶体管布置的导电和非导通操作状态。晶体管布置的导电操作状态允许在晶体管布置中形成感应回路电流，并且晶体管布置的非导通操作状态禁止晶体管布置中的感应回路电流的形成。

18. 发明申请

US20130113074A1 Capacitor system and method for producing a capacitor system 有权
公开(公告)号：US20130113074A1
公开(公告)日：2013-05-09
申请号：US13291081
申请日：2011-11-07
申请人： Frank Ebersberger , Peter Beckedahl , Hartmut Kulas , Peter Schott
发明人： Frank Ebersberger , Peter Beckedahl , Hartmut Kulas , Peter Schott
IPC分类号： H01L29/86 , H01G4/30 , H01G4/00
CPC分类号： H01G2/08 , H01G2/02 , H01G2/10 , H01G2/106 , H01G4/224 , H01L28/40 , H05K7/20927 , Y10T29/43
摘要： A capacitor system and a method for producing a capacitor system. The capacitor system may be used in a power semiconductor module. In one embodiment, the capacitor system comprises a metal shaped body having a depression; a capacitor arranged at least partly in the depression; a spacer composed of electrically insulating material, the spacer being arranged at least partly between the capacitor and the metal shaped body in the depression; and an electrically insulating potting material provided in the depression, wherein the potting material fixes the capacitor in the depression so that the capacitor does not touch the metal shaped body.

19. 发明申请

US20130062726A1 SEMICONDUCTOR FUSE WITH ENHANCED POST-PROGRAMMING RESISTANCE 有权
公开(公告)号：US20130062726A1
公开(公告)日：2013-03-14
申请号：US13231194
申请日：2011-09-13
申请人： Andreas Kurz , Maciej Wiatr
发明人： Andreas Kurz , Maciej Wiatr
IPC分类号： H01L29/86 , H01L21/265
CPC分类号： H01L23/5256 , H01L21/26506 , H01L2924/0002 , H01L2924/00
摘要： Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-κ/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-κ dielectric layer on the STI region, forming a metal gate on the high-κ dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated.

20. 发明申请

US20130056854A1 COMPLEMENTARY STRESS LINER TO IMPROVE DGO/AVT DEVICES AND POLY AND DIFFUSION RESISTORS 有权
标题翻译：补充应力衬管改善DGO / AVT器件和聚偏振电阻
公开(公告)号：US20130056854A1
公开(公告)日：2013-03-07
申请号：US13667657
申请日：2012-11-02
申请人： Stefan FLACHOWSKY , Jan HOENTSCHEL , Thilo SCHEIPER
发明人： Stefan FLACHOWSKY , Jan HOENTSCHEL , Thilo SCHEIPER
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： H01L28/20 , H01L29/78 , H01L29/7843
摘要： Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.
摘要翻译：通过使用互补应力衬垫，在长沟道半导体器件和电阻器中电子迁移率和空穴迁移率得到改善。实施例包括在衬底上形成长沟道半导体器件，并在半导体器件上形成互补应力衬垫。实施例包括在衬底上形成电阻器，并通过在电阻器上形成互补应力衬垫来调谐电阻器的电阻。使用压缩应力衬垫来改善n型器件中的电子迁移率，并且使用拉伸应力衬垫来改善p型器件中的空穴迁移率。

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