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21. 发明授权

US6049109A Silicon on Insulator semiconductor device with increased withstand voltage 失效
标题翻译：硅绝缘体半导体器件具有增加的耐受电压
公开(公告)号：US6049109A
公开(公告)日：2000-04-11
申请号：US526284
申请日：1995-09-11
申请人： Ichiro Omura , Akio Nakagawa
发明人： Ichiro Omura , Akio Nakagawa
IPC分类号： H01L27/12 , H01L29/06 , H01L29/08 , H01L29/36 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/78 , H01L29/786 , H01L29/861 , H01L29/868 , H01L27/01 , H01L31/075
CPC分类号： H01L29/7824 , H01L29/36 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/408 , H01L29/7394 , H01L29/7436 , H01L29/7813 , H01L29/78621 , H01L29/8611 , H01L29/868 , H01L29/0653 , H01L29/0878 , H01L29/78603
摘要： A power semiconductor device according to the present invention has an SOI substrate formed of a buried silicon oxide film having an uneven surface portion on the surface thereof and an n-type silicon active layer of low impurity concentration formed on the buried silicon oxide film. An n-type emitter layer and a p-type emitter layer are selectively formed in the surface area of the n-type silicon active layer. A cathode electrode and an anode electrode are respectively formed on the n-type emitter layer and p-type emitter layer. With the above structure, a power semiconductor device of high withstand voltage can be realized.
摘要翻译：根据本发明的功率半导体器件具有由其表面上具有不平坦表面部分的掩埋氧化硅膜和在掩埋氧化硅膜上形成的低杂质浓度的n型硅有源层形成的SOI衬底。在n型硅有源层的表面区域中选择性地形成n型发射极层和p型发射极层。在n型发射极层和p型发射极层上分别形成阴极电极和阳极电极。利用上述结构，可以实现高耐压的功率半导体器件。

22. 发明授权

US6025622A Conductivity modulated MOSFET 失效
公开(公告)号：US6025622A
公开(公告)日：2000-02-15
申请号：US104326
申请日：1998-06-25
申请人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
发明人： Akio Nakagawa , Hiromichi Ohashi , Yoshihiro Yamaguchi , Kiminori Watanabe , Thuneo Thukakoshi
IPC分类号： H01L29/06 , H01L29/10 , H01L29/739 , H01L29/74
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0696 , H01L29/7393 , H01L29/7395
摘要： A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

23. 发明授权

US5985708A Method of manufacturing vertical power device 失效
标题翻译：垂直功率器件的制造方法
公开(公告)号：US5985708A
公开(公告)日：1999-11-16
申请号：US816596
申请日：1997-03-13
申请人： Akio Nakagawa , Naoharu Sugiyama , Tomoko Matsudai , Norio Yasuhara , Atsusi Kurobe , Hideyuki Funaki , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Akio Nakagawa , Naoharu Sugiyama , Tomoko Matsudai , Norio Yasuhara , Atsusi Kurobe , Hideyuki Funaki , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L27/12 , H01L29/73 , H01L29/739 , H01L29/786 , H01L21/8249
CPC分类号： H01L29/78696 , H01L27/1203 , H01L29/7317 , H01L29/7394 , H01L29/78612 , H01L29/78624 , H01L29/78639 , H01L29/78645 , H01L29/78687
摘要： A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer formed on the insulating layer and having a first conducting type region and a second conducting type region, wherein the first conducting type source layer of the vertical semiconductor device and the first conducting type region of the polycrystalline semiconductor layer are simultaneously formed.
摘要翻译：一种半导体装置，包括具有第一导电型半导体衬底的垂直型半导体器件，形成在半导体衬底的表面上的漏极层，形成在漏极层的表面上的漏电极，第二导电型基极层，所述半导体衬底的与所述漏极层相对的表面，选择性地形成在所述第二导电型基极层的表面上的第一导电型源极层，形成在所述第一导电型源极层和所述第二导电型基极层上的源电极，以及通过栅极绝缘膜与第一导电型源极层，第二导电型基极层和半导体基板接触形成的栅电极，以及在半导体基板的表面的区域中形成有绝缘层的侧面半导体装置不同于第二导电型基底层，和多晶半导体层形成在绝缘层上并具有第一导电类型区域和第二导电类型区域，其中垂直半导体器件的第一导电型源极层和多晶半导体层的第一导电类型区域同时形成。

24. 发明授权

US5982015A High breakdown voltage semiconductor device 失效
公开(公告)号：US5982015A
公开(公告)日：1999-11-09
申请号：US251489
申请日：1999-02-17
申请人： Keizo Hirayama , Hideyuki Funaki , Fumito Suzuki , Akio Nakagawa
发明人： Keizo Hirayama , Hideyuki Funaki , Fumito Suzuki , Akio Nakagawa
IPC分类号： H01L29/06 , H01L29/40 , H01L29/47 , H01L29/861 , H01L29/872 , H01L27/095 , H01L29/812 , H01L31/07
CPC分类号： H01L29/404 , H01L29/0692 , H01L29/8611 , H01L29/872 , Y10S257/928
摘要： Disclosed is a high breakdown voltage semiconductor device comprising a semiconductor substrate, an active layer consisting of a high resistivity semiconductor layer of a first conductivity type formed on the substrate with an insulating layer interposed therebetween, a first impurity region of the first conductivity type formed within the active layer, a second impurity region of a second conductivity type formed within the active layer, a third impurity region of the second conductivity type formed within the second impurity region and having a high impurity concentration, a first electrode being in ohmic contact with the first impurity region and the fourth impurity region, and a second electrode being in Schottky contact with the second impurity region and in ohmic contact with the third impurity region.

25. 发明授权

US5894164A High voltage semiconductor device 失效
标题翻译：高压半导体器件
公开(公告)号：US5894164A
公开(公告)日：1999-04-13
申请号：US927691
申请日：1997-09-11
申请人： Hideyuki Funaki , Akio Nakagawa , Norio Yasuhara , Yoshinori Terazaki
发明人： Hideyuki Funaki , Akio Nakagawa , Norio Yasuhara , Yoshinori Terazaki
IPC分类号： H01L29/06 , H01L29/739 , H01L29/72
CPC分类号： H01L29/7394 , H01L29/0696
摘要： A lateral IGBT has a n-source layer and a p-contact layer both in contact with a source electrode. The source layer has a trunk adjacent to a channel region under a gate electrode, and a plurality of branches extending from its trunk to the source electrode to be in contact with the source electrode. The contact layer has a trunk in contact with the source electrode, and a plurality of branches extending from its trunk to the source layer trunk The source layer branches and the contact layer branches have shapes complementary with each other and are alternately arranged. The source layer trunk has a width La in an X direction (channel direction), which satisfies a condition, 0.5 .mu.m
摘要翻译：横向IGBT具有与源电极接触的n源层和p接触层。源极层具有与栅电极下方的沟道区域相邻的中继线，以及从其主干延伸到源极电极与源极电极接触的多个分支。接触层具有与源电极接触的干线，以及从其干线延伸到源层干线的多个分支。源极层分支和接触层分支具有彼此互补的形状并交替布置。源层干线在X方向（沟道方向）上具有宽度La，满足0.5μm

26. 发明授权

US5838026A Insulated-gate semiconductor device 失效
标题翻译：绝缘栅半导体器件
公开(公告)号：US5838026A
公开(公告)日：1998-11-17
申请号：US827530
申请日：1997-03-28
申请人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
发明人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L21/36
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译：绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

27. 发明授权

US5793065A Insulated-gate thyristor 失效
公开(公告)号：US5793065A
公开(公告)日：1998-08-11
申请号：US483325
申请日：1995-06-07
申请人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
发明人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
IPC分类号： H01L29/423 , H01L29/745 , H01L29/749 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/42308 , H01L29/749
摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

28. 发明授权

US5585651A Insulated-gate semiconductor device having high breakdown voltages 失效
标题翻译：具有高击穿电压的绝缘栅半导体器件
公开(公告)号：US5585651A
公开(公告)日：1996-12-17
申请号：US487508
申请日：1995-06-07
申请人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
发明人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a p type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译：绝缘栅半导体器件包括p型发射极层，在P型发射极层上形成的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

29. 发明授权

US5548150A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US5548150A
公开(公告)日：1996-08-20
申请号：US425246
申请日：1995-04-17
申请人： Ichiro Omura , Akio Nakagawa , Tadashi Sakai , Masayuki Sekimura , Hideyuki Funaki
发明人： Ichiro Omura , Akio Nakagawa , Tadashi Sakai , Masayuki Sekimura , Hideyuki Funaki
IPC分类号： H01F41/04 , H01L21/336 , H01L27/02 , H01L27/12 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/423 , H01L29/739 , H01L29/74 , H01L29/78 , H01L29/786 , H01L27/01
CPC分类号： H01L29/7824 , H01F41/046 , H01L27/0255 , H01L27/1203 , H01L29/0878 , H01L29/1045 , H01L29/1087 , H01L29/402 , H01L29/66772 , H01L29/7393 , H01L29/7436 , H01L29/7813 , H01L29/7816 , H01L29/7833 , H01L29/7835 , H01L29/78612 , H01L29/78618 , H01L29/78624 , H01L29/78639 , H01F2017/0086 , H01L29/0657 , H01L29/0692 , H01L29/42368 , Y10S257/901
摘要： A high-resistant p-silicon layer is formed on a silicon substrate through a silicon oxide film. N-source and n-drain layers are selectively formed in the surface of the high-resistant p-silicon layer. A gate electrode is formed through a gate insulating film on a channel region between the source and drain layers. To induce an n-inverted layer under the gate electrode, a p-base layer is formed in the high-resistant p-silicon layer. A depletion layer extending from a pn junction between the n-drain layer and the high-resistant p-silicon layer reaches the silicon oxide film in a thermal equilibrium state. Part of the high-resistant p-silicon layer extends into a channel region between the drain and base layers. The drain and base layers are connected to each other through part of the depletion layer in the thermal equilibrium state. A field effect transistor having a high-speed operation is provided.
摘要翻译：通过氧化硅膜在硅衬底上形成高电阻的p硅层。在高电阻p-硅层的表面上选择性地形成N源极和n-漏极层。在源极和漏极层之间的沟道区上通过栅极绝缘膜形成栅电极。为了在栅电极下方引入n反转层，在高电阻p-硅层中形成p基层。从n-漏层和高电阻p-硅层之间的pn结延伸的耗尽层在热平衡状态下到达氧化硅膜。部分耐高温p硅层延伸到漏极和基极层之间的沟道区域。漏极和基极层在热平衡状态下通过耗尽层的一部分彼此连接。提供具有高速操作的场效应晶体管。

30. 发明授权

US5510647A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5510647A
公开(公告)日：1996-04-23
申请号：US213027
申请日：1994-03-15
申请人： Hiroomi Nakajima , Yasuhiro Katsumata , Hiroshi Iwai , Toshihiko Iinuma , Kazumi Inou , Mitsuhiko Kitagawa , Kouhei Morizuka , Akio Nakagawa , Ichiro Omura
发明人： Hiroomi Nakajima , Yasuhiro Katsumata , Hiroshi Iwai , Toshihiko Iinuma , Kazumi Inou , Mitsuhiko Kitagawa , Kouhei Morizuka , Akio Nakagawa , Ichiro Omura
IPC分类号： H01L21/331 , H01L27/12 , H01L29/73 , H01L29/786 , H01L29/72 , H01L21/82
CPC分类号： H01L29/66265 , H01L27/1203 , H01L29/66242 , H01L29/7317 , H01L29/78654
摘要： A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is formed on the end portion of the collector layer by etching, using an aqueous KOH solution. A B-doped p-silicon layer is formed on the end face by epitaxial growth and is used as a base layer. Furthermore, an As-doped n-silicon layer is formed on the base layer and is used as an emitter layer. Electrodes are respectively connected to the collector, base, and emitter layers.
摘要翻译：在具有氧化硅膜的硅衬底上形成双极晶体管。在氧化硅膜上形成具有（100）面的顶面的n型硅层，作为集电体层使用。使用KOH水溶液通过蚀刻在集电体层的端部上形成由（111）面构成的端面。通过外延生长在端面上形成B掺杂的p硅层，并用作基底层。此外，在基极层上形成As掺杂的n硅层，并用作发射极层。电极分别连接到集电极，基极和发射极层。

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