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    • 3. 发明申请
    • POWER SEMICONDUCTOR DEVICE
    • 功率半导体器件
    • US20120068248A1
    • 2012-03-22
    • US13233993
    • 2011-09-15
    • Yusuke KAWAGUCHI
    • Yusuke KAWAGUCHI
    • H01L29/788H01L29/78
    • H01L29/7813H01L29/0626H01L29/0696H01L29/407H01L29/4236H01L29/42368H01L29/4238H01L29/7805H01L29/7808
    • According to one embodiment, a semiconductor device, includes an element unit including a vertical-type MOSFET, the vertical-type MOSFET in including a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer sequentially stacked in order, an impurity concentration of the second semiconductor layer being lower than the first semiconductor layer, an insulator covering inner surfaces of a plurality of trenches, the adjacent trenches being provided with a first interval in between, and a diode unit including basically with the units of the element unit, the adjacent trenches being provided with a second interval in between, the second interval being larger than the first interval.
    • 根据一个实施例,半导体器件包括包括垂直型MOSFET的元件单元,包括第一半导体层的垂直型MOSFET,第二半导体层,第三半导体层,第四半导体层,第五半导体层 层,所述第二半导体层的杂质浓度低于所述第一半导体层,绝缘体覆盖多个沟槽的内表面,所述相邻沟槽之间设置有第一间隔,二极管单元包括: 基本上与元件单元的单元相邻,相邻沟槽之间设置有第二间隔,第二间隔大于第一间隔。
    • 4. 发明授权
    • Semiconductor device and method for manufacturing same
    • 半导体装置及其制造方法
    • US07919811B2
    • 2011-04-05
    • US12122165
    • 2008-05-16
    • Miwako AkiyamaYusuke KawaguchiYoshihiro Yamaguchi
    • Miwako AkiyamaYusuke KawaguchiYoshihiro Yamaguchi
    • H01L29/76H01L29/94H01L31/062H01L31/113H01L31/119
    • H01L29/7813H01L21/26586H01L29/1095H01L29/41766H01L29/66727H01L29/66734
    • A semiconductor device includes a second-conductivity-type base region provided on a first-conductivity-type semiconductor layer, a first-conductivity-type source region provided on the second-conductivity-type base region, a gate insulating film covering an inner wall of a trench which passes through the second-conductivity-type base region and reaching the first-conductivity-type semiconductor layer, a gate electrode buried in the trench via the gate insulating film, and a second-conductivity-type region being adjacent to the second-conductivity-type base region below the first-conductivity-type source region, spaced from the gate insulating film, and having a higher impurity concentration than the second-conductivity-type base region. c≧d is satisfied, where d is a depth from an upper surface of the first-conductivity-type source region to a lower end of the gate electrode, and c is a depth from an upper surface of the first-conductivity-type source region to a lower surface of the second-conductivity-type base region.
    • 半导体器件包括设置在第一导电型半导体层上的第二导电型基极区域,设置在第二导电型基极区域上的第一导电型源极区域,覆盖内壁的栅极绝缘膜 通过所述第二导电型基极区域并到达所述第一导电型半导体层的沟槽,经由所述栅极绝缘膜埋设在所述沟槽中的栅电极,以及与所述第二导电型基极区相邻的第二导电型区域 与第一导电型源极区域相邻的第二导电型基极区域,与栅极绝缘膜间隔开,并且具有比第二导电型基极区域更高的杂质浓度。 c≥d,其中d是从第一导电型源极区的上表面到栅电极的下端的深度,c是从第一导电型源的上表面的深度 区域延伸到第二导电型基极区域的下表面。
    • 6. 发明授权
    • Trench-gate semiconductor device and manufacturing method of trench-gate semiconductor device
    • 沟槽栅半导体器件及沟槽栅极半导体器件的制造方法
    • US07566933B2
    • 2009-07-28
    • US11484664
    • 2006-07-12
    • Yoshihiro YamaguchiYusuke KawaguchiSyotaro Ono
    • Yoshihiro YamaguchiYusuke KawaguchiSyotaro Ono
    • H01L29/78
    • H01L29/7813H01L29/0696H01L29/1095H01L29/66734
    • Disclosed is a trench-gate semiconductor device including: a trench gate structure; a source layer having a first conductivity type, facing a gate electrode via a gate insulating film, and having a top plane; a base layer having a second conductivity type, being adjacent to the source layer, and facing the gate electrode via the gate insulating film; a semiconductor layer having the first conductivity type, being adjacent to the base layer, and facing the gate electrode via the gate insulating film without contacting the source layer; and a contact layer having the second conductivity type, contacting the source layer and base layer, having a top plane continuing with the top plane of the source layer, and having two or more peaks in an impurity concentration value profile in a depth direction from the top plane thereof, the peaks being positioned shallower than a formed depth of the source layer.
    • 公开了一种沟槽栅半导体器件,包括:沟槽栅极结构; 具有第一导电类型的源极层,经由栅极绝缘膜面对栅电极,并具有顶面; 具有第二导电类型的基底层,与源极层相邻,并且经由栅极绝缘膜面对栅电极; 具有第一导电类型的半导体层,与基底层相邻,并且经由栅极绝缘膜面对栅电极而不接触源极层; 以及具有第二导电类型的接触层,与源极层和基极层接触,具有与源极层的顶部平面连续的顶面,并且具有两个或更多个沿着深度方向的杂质浓度值分布中的峰 峰位于比源层的形成深度浅的位置。
    • 7. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20090146209A1
    • 2009-06-11
    • US12332260
    • 2008-12-10
    • Miwako AkiyamaYusuke KawaguchiYoshihiro Yamaguchi
    • Miwako AkiyamaYusuke KawaguchiYoshihiro Yamaguchi
    • H01L29/78H01L21/336
    • H01L29/7813H01L21/26586H01L29/0634H01L29/0869H01L29/0878H01L29/1095H01L29/41741H01L29/41766H01L29/66727H01L29/66734
    • A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the second conductivity type provided in an interior portion of the second semiconductor layer corresponding to a part under the contact groove. An uppermost portion of the fifth semiconductor layer contacts the third semiconductor layer, a lowermost portion of the fifth semiconductor layer has a higher impurity concentration than that of the other portion in the fifth semiconductor layer and is located in the second semiconductor layer and not contacting the first semiconductor layer, and the fifth semiconductor layer is narrower from the uppermost portion to the lower most portion.
    • 半导体器件包括:第一导电类型的第一半导体层; 第一导电类型的第二半导体层设置在第一半导体层的主表面上并且具有比第一半导体层的杂质浓度低的第二半导体层; 设置在第二半导体层上的第二导电类型的第三半导体层; 选择性地设置在第三半导体层上的第一导电类型的第四半导体层; 设置在穿过所述第三半导体层并到达所述第二半导体层的沟槽中的栅电极; 与所述第四半导体层接触的第一主电极,并且通过设置成在所述连续的栅电极之间穿过所述第四半导体层的接触槽使所述第三半导体层接触; 设置在与所述第一半导体层的主表面相反的表面上的第二主电极; 以及第二导电类型的第五半导体层,设置在与所述接触槽下方的部分对应的所述第二半导体层的内部。 第五半导体层的最上部与第三半导体层接触,第五半导体层的最下部分的杂质浓度比第五半导体层中的其他部分杂质浓度高,位于第二半导体层中, 第一半导体层,第五半导体层从最上部到最下部较窄。
    • 8. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07541643B2
    • 2009-06-02
    • US11399448
    • 2006-04-07
    • Syotaro OnoWataru SaitoYusuke Kawaguchi
    • Syotaro OnoWataru SaitoYusuke Kawaguchi
    • H01L29/76H01L29/94
    • H01L29/7813H01L29/0615H01L29/063H01L29/0634H01L29/402H01L29/41741H01L29/7811
    • This semiconductor device comprises a pillar layer including a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type formed alternately on a first semiconductor layer. At the same depth position in the device region and the end region, a difference between an impurity concentration [cm-3] of the second semiconductor pillar layer in the device region and that of the second semiconductor pillar layer in the end region is less than plus or minus 5%. A width W11 [um] of the first semiconductor pillar layer in the device region, a width W21 [um] of the second semiconductor pillar layer in the device region, a width W12 [um] of the first semiconductor pillar layer in the end region, and a width W22 [um] of the second semiconductor pillar layer in the end region, meet the relationship of W21/W11
    • 该半导体器件包括:交替地在第一半导体层上形成的包括第一导电类型的第一半导体柱层和第二导电类型的第二半导体柱层的柱层。 在器件区域和端部区域的相同深度位置处,器件区域中的第二半导体柱层的杂质浓度[cm-3]与末端区域中的第二半导体柱层的杂质浓度[cm-3]之间的差小于 加或减5%。 器件区域中的第一半导体柱层的宽度W11 [μm],器件区域中的第二半导体柱层的宽度W21 [μm],端部区域中的第一半导体柱层的宽度W12 [μm] ,并且端部区域中的第二半导体柱层的宽度W22 [μm]满足W21 / W11
    • 10. 发明申请
    • TRENCH-GATED MOSFET INCLUDING SCHOTTKY DIODE THEREIN
    • 包含肖特基二极管的TRENCH-GFET MOSFET
    • US20070194372A1
    • 2007-08-23
    • US11740045
    • 2007-04-25
    • Syotaro OnoAkio NakagawaYusuke KawaguchiYoshihiro Yamaguchi
    • Syotaro OnoAkio NakagawaYusuke KawaguchiYoshihiro Yamaguchi
    • H01L31/00
    • H01L29/7813H01L29/1095
    • Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
    • 公开了一种沟槽MOSFET,其包括:具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层,其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层,其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层,以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层,与p型基底层和金属层接触。