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    • 22. 发明申请
    • TRANSPORT SUBSYSTEM FOR AN MBIST CHAIN ARCHITECTURE
    • 用于MBIST链架构的运输子系统
    • US20090307543A1
    • 2009-12-10
    • US12183512
    • 2008-07-31
    • Alexandre AndreevAnatoli BolotovMikhail Grinchuk
    • Alexandre AndreevAnatoli BolotovMikhail Grinchuk
    • G11C29/12G06F11/27
    • G11C29/48G11C29/1201G11C29/26G11C29/32G11C2029/2602G11C2029/5602
    • An apparatus comprising a controller, a plurality of transport circuits and a plurality of memory-controlling circuits. The controller may be configured to (i) present one or more commands and (ii) receive one or more responses. Each of the plurality of transport circuits may be configured to (i) receive one of the commands, (ii) present the responses, and (iii) generate one or more control signals. Each of the plurality of memory-controlling circuits may be (i) coupled to a respective one of the plurality of transport circuits and (ii) configured to (i) generate one or more memory access signals in response to the one or more control signals, (ii) receive one or more memory output signals from a respective memory in response to the one or more memory access signals and (iii) generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits.
    • 一种装置,包括控制器,多个传输电路和多个存储器控制电路。 控制器可以被配置为(i)呈现一个或多个命令,并且(ii)接收一个或多个响应。 多个传输电路中的每一个可以被配置为(i)接收命令之一,(ii)呈现响应,以及(iii)产生一个或多个控制信号。 多个存储器控制电路中的每一个可以(i)耦合到多个传输电路中的相应一个,并且(ii)被配置为(i)响应于一个或多个控制信号而产生一个或多个存储器访问信号 ,(ii)响应于所述一个或多个存储器访问信号,从相应存储器接收一个或多个存储器输出信号,以及(iii)响应于所述一个或多个存储器输出信号产生响应。 各个存储器可以独立地定尺寸。 控制器通常为每个相应的存储器提供通用的测试程序,这些存储器可以通过存储器控制电路为每个相应的存储器的大小进行调整。