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21. 发明申请

US20110058433A1 LATENCY CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD FOR CONTROLLING LATENCY 失效
标题翻译：延迟控制电路，包括其的半导体存储器件以及控制延迟的方法
公开(公告)号：US20110058433A1
公开(公告)日：2011-03-10
申请号：US12633387
申请日：2009-12-08
申请人： Hae-Rang Choi , Yong-ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hae-Rang Choi , Yong-ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C7/22 , H03L7/00
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C2207/2272
摘要： A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information.
摘要翻译：延迟控制电路包括路径计算器，被配置为计算输入信号在芯片内经过的路径的延迟值，并输出延迟值作为路径信息;延迟值计算器，被配置为输出表示延迟值的延迟信息用于基于所述输入信号和所述路径信息的等待时间值延迟所述输入信号;以及延迟器，被配置为将所述输入信号延迟与所述延迟信息相对应的延迟。

22. 发明申请

US20110001533A1 SAMPLING CIRCUIT 有权
标题翻译：采样电路
公开(公告)号：US20110001533A1
公开(公告)日：2011-01-06
申请号：US12630021
申请日：2009-12-03
申请人： Ji-Wang LEE , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang LEE , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03K3/00 , G06F7/42 , G06G7/12
CPC分类号： H03K3/356139 , G06F5/06 , H03K3/0375
摘要： A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.
摘要翻译：一种用于半导体器件的采样电路，包括：第一采样单元，被配置为与参考时钟信号同步地采样数据信号并输出第一输出信号;第二采样单元，被配置为与延迟数据信号同步采样参考时钟信号并输出第二输出信号，以及输出单元，被配置为组合第一和第二输出信号并输出采样数据信号。

23. 发明授权

US07852243B2 Receiver circuit 有权
标题翻译：接收电路
公开(公告)号：US07852243B2
公开(公告)日：2010-12-14
申请号：US12179486
申请日：2008-07-24
申请人： Tae-Jin Hwang , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang
发明人： Tae-Jin Hwang , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang
IPC分类号： H03M1/06
CPC分类号： G06F13/4072
摘要： A receiver circuit is capable of improving its operating characteristics. The receiver circuit includes a variable converter configured to output off-set control voltages in a first output range in a first operation mode and output the off-set control voltages in a second output range in a second operation mode according to a test mode activation signal, and a sense amplifier configured to sense input data based on a sensitivity, wherein the sensitivity is controlled by the off-set control voltages.
摘要翻译：接收机电路能够改善其操作特性。接收器电路包括可变转换器，其被配置为在第一操作模式中在第一输出范围中输出偏移控制电压，并且根据测试模式激活信号在第二操作模式中将偏移控制电压输出到第二输出范围以及感测放大器，被配置为基于灵敏度来感测输入数据，其中灵敏度由偏移控制电压控制。

24. 发明授权

US07852131B2 Receiver circuit of semiconductor memory apparatus 失效
标题翻译：半导体存储器的接收电路
公开(公告)号：US07852131B2
公开(公告)日：2010-12-14
申请号：US12175224
申请日：2008-07-17
申请人： Tae-Jin Hwang , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee
发明人： Tae-Jin Hwang , Kun-Woo Park , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： H03L7/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and controlling setup/hold time of the first output signal based on a level of a first offset voltage, a level converter configured to control a voltage level of the first output signal according to a first code, and a second phase transmission unit configured to receive an output signal of the level converter for as a second offset voltage while being synchronized with a second clock signal, to generate a second output signal by detecting the input data according to the detection levels, and to control setup/hold time of the second output signal.
摘要翻译：能够控制建立/保持时间的接收机电路包括：第一相位发送单元，被配置为通过在与第一时钟信号同步的同时根据多个检测电平检测输入数据来生成第一输出信号，以及控制第一输入信号的建立/保持时间基于第一偏移电压的电平的输出信号，被配置为根据第一代码来控制第一输出信号的电压电平的电平转换器;以及第二相位发送单元，被配置为接收电平转换器的输出信号作为第二偏移电压，同时与第二时钟信号同步，通过根据检测电平检测输入数据产生第二输出信号，并控制第二输出信号的建立/保持时间。

25. 发明申请

US20100277209A1 SIGNAL RECEIVER CIRCUIT CAPABLE OF IMPROVING AREA AND POWER EFFICIENCY IN SEMICONDUCTOR INTEGRATED CIRCUITS 有权
标题翻译：提高半导体集成电路面积和功率效率的信号接收电路
公开(公告)号：US20100277209A1
公开(公告)日：2010-11-04
申请号：US12770706
申请日：2010-04-29
申请人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
发明人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H03L7/00 , H03L5/00
CPC分类号： H03K5/08 , H03K3/356139 , H03K3/356191 , H04L25/062
摘要： A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.
摘要翻译：信号接收器电路包括第一电平检测器，用于响应于一对第一参考信号偏移控制第一输出节点。第二级检测器偏移 - 响应于一对第二参考信号来控制第二输出节点。

26. 发明授权

US07821311B2 Delay locked loop circuit and memory device having the same 有权
标题翻译：延迟锁定环电路和具有相同的存储器件
公开(公告)号：US07821311B2
公开(公告)日：2010-10-26
申请号：US12346614
申请日：2008-12-30
申请人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0995 , H03L7/0998
摘要： A DLL circuit includes a multiphase clock signal generating unit configured to produce a plurality of multiphase clock signals by delaying a reference clock signal for a unit delay time and to produce an enable signal that is enabled when one of the plurality of the multiphase clock signals synchronizes with the reference clock signal at a frequency, and a multiphase clock signal selecting unit configured to delay one of the plurality of the multiphase clock signals for a predetermined time in response to a first control signal, to compare a phase of a delayed multiphase clock signal with a phase of the reference clock signal, and to output one of the plurality of the multiphase clock signals as a delayed clock signal, wherein a phase of the delayed clock signal synchronizes with the phase of the reference clock signal when the enable signal is enabled.
摘要翻译：一个DLL电路包括一个多相时钟信号产生单元，被配置为通过延迟基准时钟信号来产生一个单位延迟时间来产生多个多相时钟信号，并产生一个使能信号，当多个多相时钟信号中的一个同步时以及频率上的参考时钟信号，以及多相时钟信号选择单元，被配置为响应于第一控制信号而延迟多个多相时钟信号中的一个预定时间，以比较延迟的多相时钟信号的相位具有参考时钟信号的相位，并且将多个多相时钟信号中的一个作为延迟的时钟信号输出，其中当使能信号被使能时，延迟的时钟信号的相位与参考时钟信号的相位同步。

27. 发明授权

US07755410B2 Semiconductor integrated circuit capable of overcoming clock signal jitter 失效
标题翻译：能够克服时钟信号抖动的半导体集成电路
公开(公告)号：US07755410B2
公开(公告)日：2010-07-13
申请号：US12330287
申请日：2008-12-08
申请人： Ic-Su Oh , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Ic-Su Oh , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G06F1/04
CPC分类号： H03K5/133 , H03K5/003 , H03K5/156
摘要： A semiconductor integrated circuit includes a voltage supplying unit that supplies a first regulated voltage and a second regulated voltage by using a first reference voltage and a second reference voltage, respectively, and a clock buffer unit that supplies an output clock clocking within a range of the first regulated voltage and the second regulated voltage.
摘要翻译：一种半导体集成电路包括分别通过使用第一参考电压和第二参考电压来提供第一调节电压和第二调节电压的电压提供单元，以及时钟缓冲器单元，其提供在第一调节电压和第二调节电压。

28. 发明申请

US20100164571A1 PHASE MIXER AND DELAY LOCKED LOOP INCLUDING THE SAME 有权
标题翻译：相位混合器和延迟锁定环路，包括它们
公开(公告)号：US20100164571A1
公开(公告)日：2010-07-01
申请号：US12347298
申请日：2008-12-31
申请人： Jae-Min JANG , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
发明人： Jae-Min JANG , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
IPC分类号： H03L7/06 , G06G7/12
CPC分类号： H03L7/0814 , H03K5/13 , H03K2005/00052 , H03K2005/00065 , H03L7/0818
摘要： A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.
摘要翻译：相位混合器包括：相位混合单元，被配置为响应于相位控制信号混合第一输入信号的相位和第二输入信号的相位，并输出相位混合信号，该相位混合信号的相位由一个或多个单位单位相位值，以及相位值调整单元，被配置为控制短语混合单元的操作，使得响应于代码信号来编码单位相位值，编码信号编码处理，电压或温度（PVT）变化中的至少一个。

29. 发明申请

US20100090726A1 DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路的数据接收器
公开(公告)号：US20100090726A1
公开(公告)日：2010-04-15
申请号：US12636922
申请日：2009-12-14
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： G01R19/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A data receiver of a semiconductor integrated circuit is configured to detect received data using an equalization function, wherein the data receiver is configured to stop the equalization function during a period in which the data is not received.
摘要翻译：半导体集成电路的数据接收器被配置为使用均衡功能检测接收到的数据，其中数据接收器被配置为在未接收到数据的时段期间停止均衡功能。

30. 发明授权

US07696799B2 Delay cell of voltage controlled delay line using digital and analog control scheme 有权
标题翻译：使用数字和模拟控制方案延时电压延时线
公开(公告)号：US07696799B2
公开(公告)日：2010-04-13
申请号：US12283810
申请日：2008-09-15
申请人： Yong-Ju Kim
发明人： Yong-Ju Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0891
摘要： Provided is an analog/digital control delay locked loop (DLL). The DLL includes a phase detector for detecting a phase difference between an input clock signal and a feedback signal to provide an up detection signal or a down detection signal, a charge pump for generating an adjusted output current based on the up or down signals, a loop filter for low pass-filtering the output current to produce an analog control voltage, a voltage controlled delay Line (VCDL) for receiving the analog control voltage, the input clock signal and a digital code, and delaying the input clock signal based on the analog control voltage and the digital code to provide an output clock signal, a delay replica modeling unit formed by replica of delay factors for producing the feedback signal depending on the output clock signal, and a digital code generator for generating the digital code.
摘要翻译：提供了一种模拟/数字控制延迟锁定环（DLL）。该DLL包括用于检测输入时钟信号和反馈信号之间的相位差以提供上行检测信号或下降检测信号的相位检测器，用于基于上或下信号产生经调整的输出电流的电荷泵，环路滤波器，用于对输出电流进行低通滤波以产生模拟控制电压，用于接收模拟控制电压的电压控制延迟线（VCDL），输入时钟信号和数字代码，并且基于输入时钟信号延迟输入时钟信号模拟控制电压和数字代码以提供输出时钟信号，由延迟因子的副本形成的延迟复制模型单元，用于根据输出时钟信号产生反馈信号;以及数字码发生器，用于产生数字码。

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