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21. 发明授权

US07868894B2 Operand multiplexor control modifier instruction in a fine grain multithreaded vector microprocessor 失效
标题翻译：精细多线程向量微处理器中的操作数多路复用器控制修改器指令
公开(公告)号：US07868894B2
公开(公告)日：2011-01-11
申请号：US11564072
申请日：2006-11-28
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06T1/00
CPC分类号： G06T1/20
摘要： The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve rearranging vector operands in one or more source registers prior to performing vector operations. Typically, rearranging of operands in source registers is done by issuing a plurality of permute instructions that require excessive usage of temporary registers. Furthermore, the permute instructions may cause dependencies between instructions executing in a pipeline, thereby adversely affecting performance. Embodiments of the invention provide a level of muxing between a register file and a vector unit that allow for rearrangement of vector operands in source registers prior to providing the operands to the vector unit, thereby obviating the need for permute instructions.
摘要翻译：本发明通常涉及图像处理领域，更具体地涉及用于处理图像的指令集。矢量处理可以包括在执行向量操作之前在一个或多个源寄存器中重新排列向量操作数。通常，通过发出需要临时寄存器过度使用的多个置换指令来完成源寄存器中操作数的重新排列。此外，置换指令可能导致在流水线中执行的指令之间的相关性，从而不利地影响性能。本发明的实施例提供了一种在寄存器文件和向量单元之间的复用水平，其允许在将操作数提供给向量单元之前重新排列源寄存器中的向量操作数，从而避免了对置换指令的需要。

22. 发明授权

US07809925B2 Processing unit incorporating vectorizable execution unit 有权
标题翻译：具有可向量化执行单元的处理单元
公开(公告)号：US07809925B2
公开(公告)日：2010-10-05
申请号：US11952193
申请日：2007-12-07
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F15/80
CPC分类号： G06F15/8015 , G06F9/30036 , G06F9/30109 , G06F9/3012 , G06F9/30189 , G06F9/3802 , G06F9/3851 , G06F9/3885 , G06F9/3891 , G06F15/8061
摘要： A vectorizable execution unit is capable of being operated in a plurality of modes, with the processing lanes in the vectorizable execution unit grouped into different combinations of logical execution units in different modes. By doing so, processing lanes can be selectively grouped together to operate as different types of vector execution units and/or scalar execution units, and if desired, dynamically switched during runtime to process various types of instruction streams in a manner that is best suited for each type of instruction stream. As a consequence, a single vectorizable execution unit may be configurable, e.g., via software control, to operate either as a vector execution or a plurality of scalar execution units.
摘要翻译：可矢量化执行单元能够以多种模式操作，可矢量化执行单元中的处理通道被分组成不同模式的逻辑执行单元的不同组合。通过这样做，处理通道可以选择性地组合在一起以作为不同类型的向量执行单元和/或标量执行单元来操作，并且如果需要，在运行时期间以最适合于以下方式处理各种类型的指令流的方式进行动态切换每种类型的指令流。因此，单个可矢量化执行单元可以例如通过软件控制来配置，以作为向量执行或多个标量执行单元来操作。

23. 发明申请

US20090228682A1 Processing Unit Incorporating Special Purpose Register for Use with Instruction-Based Persistent Vector Multiplexer Control 失效
标题翻译：包含专用寄存器的处理单元，用于基于指令的持续矢量复用器控制
公开(公告)号：US20090228682A1
公开(公告)日：2009-09-10
申请号：US12045222
申请日：2008-03-10
申请人： Eric Oliver Mejdrich , Adam James Muff , Robert Allen Shearer , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Robert Allen Shearer , Matthew Ray Tubbs
IPC分类号： G06F9/30 , G06F15/76
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30123
摘要： A software-accessible special purpose register is architected into a processing unit in order to implement persistent vector multiplexer control of a vector-based execution unit. A persistent swizzle instruction is defined in an instruction set for the vector-based execution unit and is used to cause state information to be stored in the special purpose register such that the operand vectors processed by subsequent vector instructions executed by the vector-based execution unit will be selectively shuffled using the persisted state information. As a result, when multiple vector instructions require a common custom word ordering for one or more operand vectors, a single persistent swizzle instruction may be used to select the desired custom word ordering for all of the vector instructions.
摘要翻译：软件可访问专用寄存器被设计成处理单元，以便实现基于向量的执行单元的持久矢量多路复用器控制。在基于向量的执行单元的指令集中定义持续转换指令，并且用于使状态信息存储在专用寄存器中，使得由基于向量的执行单元执行的后续向量指令处理的操作数向量将使用持久状态信息选择性地进行混洗。因此，当多个向量指令需要一个或多个操作数向量的公共自定义单词排序时，可以使用单个持续旋转指令来选择所有向量指令的期望的定制单词排序。

24. 发明申请

US20090015589A1 Store Misaligned Vector with Permute 失效
标题翻译：存储不对齐向量与Permute
公开(公告)号：US20090015589A1
公开(公告)日：2009-01-15
申请号：US11775999
申请日：2007-07-11
申请人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
发明人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06T15/10
CPC分类号： G06T15/06
摘要： Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized.
摘要翻译：本发明的实施例提供处理器和存储器阵列之间的存储数据路径内的逻辑。逻辑可以被配置为在向量数据存储到存储器时将其对准。通过在将矢量数据存储到存储器时将其对准，存储器带宽可以最大化，而存储向量数据不对齐所需的处理带宽最小化。此外，本发明的实施例提供了负载数据路径内的逻辑，其允许存储的未对准的矢量数据在被加载到向量寄存器中时被对准。通过在将其加载到向量寄存器中时对准未对齐的矢量数据，可以最大化存储器带宽，同时可以最小化对准未对齐矢量数据所需的处理带宽。

25. 发明申请

US20080082784A1 Area Optimized Full Vector Width Vector Cross Product 审中-公开
标题翻译：区域优化全矢量宽度矢量交叉乘积
公开(公告)号：US20080082784A1
公开(公告)日：2008-04-03
申请号：US11925064
申请日：2007-10-26
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F15/76
CPC分类号： G06T15/06 , G06T2200/28
摘要： The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data from a common register file. The vector units may independently and simultaneously process instructions. Furthermore, the vector units may be adapted to perform scalar operations thereby integrating the vector and scalar processing. The vector units may also be configured to share resources to perform an operation, for example, a cross product operation.
摘要翻译：本发明通常涉及集成电路装置，更具体地涉及图像处理领域的方法，系统和设计结构，更具体地涉及用于支持图像处理的矢量单元。描述了双向量单元实现，其中配置了两个向量单元从公共寄存器文件接收数据。向量单元可以独立地并且同时处理指令。此外，矢量单元可以适于执行标量运算，从而整合向量和标量处理。矢量单元还可以被配置为共享资源以执行操作，例如交叉产品操作。

26. 发明申请

US20080082783A1 Dual Independent and Shared Resource Vector Execution Units with Shared Register File 有权
标题翻译：具有共享寄存器文件的双独立和共享资源向量执行单元
公开(公告)号：US20080082783A1
公开(公告)日：2008-04-03
申请号：US11924980
申请日：2007-10-26
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F9/02 , G06F15/76
CPC分类号： G06T1/20 , G06F15/8092 , G06T15/005
摘要： The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data from a common register file. The vector units may independently and simultaneously process instructions. Furthermore, the vector units may be adapted to perform scalar operations thereby integrating the vector and scalar processing. The vector units may also be configured to share resources to perform an operation, for example, a cross product operation.
摘要翻译：本发明通常涉及集成电路装置，更具体地涉及图像处理领域的方法，系统和设计结构，更具体地涉及用于支持图像处理的矢量单元。描述了双向量单元实现，其中配置了两个向量单元从公共寄存器文件接收数据。向量单元可以独立地并且同时处理指令。此外，矢量单元可以适于执行标量运算，从而整合向量和标量处理。矢量单元还可以被配置为共享资源以执行操作，例如交叉产品操作。

27. 发明授权

US09495724B2 Single precision vector permute immediate with “word” vector write mask 有权
标题翻译：单精度矢量立即与“字”向量写入掩码
公开(公告)号：US09495724B2
公开(公告)日：2016-11-15
申请号：US11554794
申请日：2006-10-31
申请人： Eric Oliver Mejdrich , Adam James Muff
发明人： Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06T1/60 , G06F9/30
CPC分类号： G06T1/60 , G06F9/30032 , G06F9/30036
摘要： The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve performing a plurality of permute operations to arrange vector operands in desired locations of a register prior to performing vector operation, for example, a cross product. The permute instructions may be dependent on one another and may require the use of temporary registers. Embodiments of the invention provide a permute instruction wherein a mask field may be used to specify a particular location of a target register in which to transfer data, thereby reducing the number of instructions for arranging data, reducing dependencies between instructions, and the usage of temporary registers.
摘要翻译：本发明通常涉及图像处理领域，更具体地涉及用于处理图像的指令集。矢量处理可以包括执行多个置换操作，以在执行矢量操作之前（例如，交叉乘积）将向量操作数布置在寄存器的期望位置中。置换指令可能彼此依赖，可能需要使用临时寄存器。本发明的实施例提供了一种置换指令，其中掩模字段可以用于指定目标寄存器的特定位置，其中传送数据，从而减少用于排列数据的指令的数量，减少指令之间的依赖性以及临时的使用注册

28. 发明授权

US08332452B2 Single precision vector dot product with “word” vector write mask 失效
标题翻译：具有单词向量写入掩码的单精度矢量点积
公开(公告)号：US08332452B2
公开(公告)日：2012-12-11
申请号：US11554774
申请日：2006-10-31
申请人： Eric Oliver Mejdrich , Adam James Muff
发明人： Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06F7/38
CPC分类号： G06F17/16
摘要： The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve performing a plurality of dot product operations to generate operands for generating operands for a new vector. The dot product operations may require the issue of a plurality of permute instructions to arrange the vector operands in desired locations of a target register. Embodiments of the invention provide a dot product instruction wherein a mask field may be used to specify a particular location of a target register in which to transfer data, thereby avoiding the need for permute instructions for arranging data, reducing dependencies between instructions, and the usage of temporary registers.
摘要翻译：本发明通常涉及图像处理领域，更具体地涉及用于处理图像的指令集。矢量处理可以涉及执行多个点积运算以产生用于生成新向量的操作数的操作数。点产品操作可能需要发出多个置换指令以将向量操作数布置在目标寄存器的期望位置中。本发明的实施例提供一种点积指令，其中掩模字段可用于指定在其中传送数据的目标寄存器的特定位置，从而避免需要用于排列数据的置换指令，减少指令之间的依赖关系和使用的临时寄存器。

29. 发明授权

US07783860B2 Load misaligned vector with permute and mask insert 失效
标题翻译：加载不对齐矢量与置换和掩码插入
公开(公告)号：US07783860B2
公开(公告)日：2010-08-24
申请号：US11830920
申请日：2007-07-31
申请人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
发明人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06F9/312
CPC分类号： G06F9/30032 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3816 , G06F9/3824
摘要： Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized.
摘要翻译：本发明的实施例提供处理器和存储器阵列之间的存储数据路径内的逻辑。逻辑可以被配置为在向量数据存储到存储器时将其对准。通过在将矢量数据存储到存储器时将其对准，存储器带宽可以最大化，而存储向量数据不对齐所需的处理带宽最小化。此外，本发明的实施例提供了负载数据路径内的逻辑，其允许存储的未对准的矢量数据在被加载到向量寄存器中时被对准。通过在将其加载到向量寄存器中时对准未对齐的矢量数据，可以最大化存储器带宽，同时可以最小化对准未对齐矢量数据所需的处理带宽。

30. 发明申请

US20100100712A1 Multi-Execution Unit Processing Unit with Instruction Blocking Sequencer Logic 失效
标题翻译：具有指令阻塞定序器逻辑的多执行单元处理单元
公开(公告)号：US20100100712A1
公开(公告)日：2010-04-22
申请号：US12252541
申请日：2008-10-16
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/22 , G06F9/3009 , G06F9/3851 , G06F9/3867
摘要： A processing unit includes multiple execution units and sequencer logic that is disposed downstream of instruction buffer logic, and that is responsive to a sequencer instruction present in an instruction stream. In response to such an instruction, the sequencer logic issues a plurality of instructions associated with a long latency operation to one execution unit, while blocking instructions from the instruction buffer logic from being issued to that execution unit. In addition, the blocking of instructions from being issued to the execution unit does not affect the issuance of instructions to any other execution unit, and as such, other instructions from the instruction buffer logic are still capable of being issued to and executed by other execution units even while the sequencer logic is issuing the plurality of instructions associated with the long latency operation.
摘要翻译：处理单元包括多个执行单元和定序器逻辑，其布置在指令缓冲器逻辑的下游，并且响应于指令流中存在的定序器指令。响应于这样的指令，定序器逻辑向一个执行单元发出与长等待时间操作相关联的多个指令，同时阻止来自指令缓冲器逻辑的指令被发送到该执行单元。此外，指令的阻塞被发布到执行单元不影响向任何其他执行单元发出指令，因此来自指令缓冲器逻辑的其他指令仍然能够被发出并由其他执行执行即使当定序器逻辑发出与长延迟操作相关联的多个指令时。

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