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1. 发明授权

US08140829B2 Multithreaded processor and method for switching threads by swapping instructions between buffers while pausing execution 失效
标题翻译：多线程处理器和通过在暂停执行时在缓冲器之间交换指令来切换线程的方法
公开(公告)号：US08140829B2
公开(公告)日：2012-03-20
申请号：US10717747
申请日：2003-11-20
申请人： Richard James Eickemeyer , David Arnold Luick
发明人： Richard James Eickemeyer , David Arnold Luick
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A processor includes primary threads of execution that may simultaneously issue instructions, and one or more backup threads. When a primary thread stalls, the contents of its instruction buffer may be switched with the instruction buffer for a backup thread, thereby allowing the backup thread to begin execution. This design allows two primary threads to issue simultaneously, which allows for overlap of instruction pipeline latencies. This design further allows a fast switch to a backup thread when a primary thread stalls, thereby providing significantly improved throughput in executing instructions by the processor.
摘要翻译：处理器包括可以同时发出指令的主执行线程以及一个或多个备用线程。当主线程停顿时，其指令缓冲器的内容可以用备用线程的指令缓冲器切换，从而允许备份线程开始执行。此设计允许两个主线程同时发出，这允许指令管线延迟的重叠。该设计还允许在主线程停止时快速切换到备用线程，从而在由处理器执行指令时提供显着提高的吞吐量。

2. 发明授权

US08001361B2 Structure for a single shared instruction predecoder for supporting multiple processors 有权
标题翻译：用于支持多个处理器的单个共享指令预解码器的结构
公开(公告)号：US08001361B2
公开(公告)日：2011-08-16
申请号：US12047901
申请日：2008-03-13
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F9/30
CPC分类号： G06F9/382 , G06F9/3828 , G06F9/3838 , G06F9/3853 , G06F9/3857 , G06F9/3859 , G06F9/3869 , G06F9/3889
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for improved techniques for executing instructions in a pipelined manner is provided. Such techniques may reduce stalls that occur when executing dependent instructions. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times.
摘要翻译：提供了一种体现在机器可读存储介质中的设计结构，用于设计，制造和/或测试用于以流水线方式执行指令的改进技术的设计。这样的技术可以减少在执行相关指令时发生的停顿。可以通过利用具有相对于彼此延迟的执行单元的管道的级联排列来减少停顿。这种级联延迟安排允许在普通问题组中发布相关指令，方法是调度它们以在不同管道中执行以在不同时间执行。

3. 发明授权

US07865769B2 In situ register state error recovery and restart mechanism 失效
标题翻译：原位寄存器状态错误恢复和重启机制
公开(公告)号：US07865769B2
公开(公告)日：2011-01-04
申请号：US11769184
申请日：2007-06-27
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F11/00
CPC分类号： G06F11/1407 , G06F9/30101 , G06F9/30105 , G06F9/30116 , G06F9/3013 , G06F9/382 , G06F9/3828 , G06F9/3842 , G06F9/3853 , G06F9/3857 , G06F9/3865 , G06F9/3869 , G06F9/3889 , G06F11/1008
摘要： Embodiments of the invention relate to methods and systems for error detection and recovery from errors during pipelined execution of data. A cascaded, delayed execution pipeline may be implemented to maintain a precise machine state. In some embodiments, a delay of one or more clock cycles may be inserted prior to a write back stage of each pipeline to facilitate error detection and recovery. Because a precise machine state is maintained error detection and recovery mechanisms may be built directly into register files of the system. If an error is detected execution of the instruction associated with the error and all subsequent instructions may be restarted.
摘要翻译：本发明的实施例涉及用于在流水线执行数据期间的错误检测和恢复的方法和系统。可以实现级联的延迟执行管线以保持精确的机器状态。在一些实施例中，可以在每个管道的回写阶段之前插入一个或多个时钟周期的延迟，以便于错误检测和恢复。因为保持精确的机器状态，错误检测和恢复机制可以直接构建到系统的寄存器文件中。如果检测到错误，可能会重新执行与错误相关的指令和所有后续指令。

4. 发明申请

US20090106526A1 Scalar Float Register Overlay on Vector Register File for Efficient Register Allocation and Scalar Float and Vector Register Sharing 审中-公开
标题翻译：矢量寄存器文件中的标量浮点寄存器覆盖，用于高效的寄存器分配和标量浮点和矢量寄存器共享
公开(公告)号：US20090106526A1
公开(公告)日：2009-04-23
申请号：US11876056
申请日：2007-10-22
申请人： David Arnold Luick , Eric Oliver Mejdrieh
发明人： David Arnold Luick , Eric Oliver Mejdrieh
IPC分类号： G06F15/76 , G06F9/02 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30109
摘要： Embodiments of the invention are generally related to image processing, and more specifically to register files for supporting image processing. An integrated register file is also provided for storing vector and scalar data. Therefore, the transfer of data to memory to exchange data between independent vector and scalar units is obviated.
摘要翻译：本发明的实施例通常涉及图像处理，更具体地涉及用于支持图像处理的寄存器文件。还提供了用于存储向量和标量数据的集成寄存器文件。因此，消除了将数据传输到存储器以在独立向量和标量单位之间交换数据。

5. 发明申请

US20090037694A1 Load Misaligned Vector with Permute and Mask Insert 失效
标题翻译：加载不对齐矢量与Permute和Mask插入
公开(公告)号：US20090037694A1
公开(公告)日：2009-02-05
申请号：US11830920
申请日：2007-07-31
申请人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
发明人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06F9/315
CPC分类号： G06F9/30032 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3816 , G06F9/3824
摘要： Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized.
摘要翻译：本发明的实施例提供处理器和存储器阵列之间的存储数据路径内的逻辑。逻辑可以被配置为在向量数据存储到存储器时将其对准。通过在将矢量数据存储到存储器时将其对准，存储器带宽可以最大化，而存储向量数据不对齐所需的处理带宽最小化。此外，本发明的实施例提供了负载数据路径内的逻辑，其允许存储的未对准的矢量数据在被加载到向量寄存器中时被对准。通过在将其加载到向量寄存器中时对准未对齐的矢量数据，可以最大化存储器带宽，同时可以最小化对准未对齐矢量数据所需的处理带宽。

6. 发明申请

US20090006768A1 Method and Apparatus for Accessing a Split Cache Directory 失效
标题翻译：用于访问分割缓存目录的方法和装置
公开(公告)号：US20090006768A1
公开(公告)日：2009-01-01
申请号：US11770099
申请日：2007-06-28
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0802 , G06F12/0897 , G06F12/1063 , G06F2212/1016
摘要： A method and apparatus for accessing a cache. The method includes receiving a request to access the cache. The request includes an address of requested data to be accessed. The method also includes using a first portion of the address to perform an access to a first directory for the cache and using a second portion of the address to perform an access to a second directory for the cache. Results from the access to the first directory for the cache and results from the access to the second directory for the cache are used to determine whether the cache includes the requested data to be accessed.
摘要翻译：一种用于访问高速缓存的方法和装置。该方法包括接收访问高速缓存的请求。请求包括要访问的请求数据的地址。该方法还包括使用地址的第一部分来执行对高速缓存的第一目录的访问，并且使用地址的第二部分来执行对高速缓存的第二目录的访问。用于访问高速缓存的第一目录的结果和用于高速缓存的第二目录的访问的结果用于确定高速缓存是否包括要访问的请求的数据。

7. 发明授权

US07065694B2 Adaptive runtime repairable entry register file 失效
标题翻译：自适应运行时修复输入寄存器文件
公开(公告)号：US07065694B2
公开(公告)日：2006-06-20
申请号：US10670713
申请日：2003-09-25
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F11/00
CPC分类号： G06F11/1032 , G11C29/76
摘要： Methods and apparatus are disclosed that provide for improved addressing of a register file in a computer system. The register file has one or more redundant words. A logical address in an instruction is mapped, during a predecode operation, to a physical address having a larger address space than the logical address. Addresses of nonfaulty words are mapped to the same word in the larger address space as the logical address. Logical addresses that point to faulty words are mapped to a redundant word that is in the larger address space but not in the address space of the logical address. Because all addresses presented to a register file decoder at access time point to nonfaulty words, no delay penalty associated with address compare during the access time is required.
摘要翻译：公开了提供计算机系统中的寄存器文件的改进寻址的方法和装置。寄存器文件有一个或多个冗余字。在预解码操作期间，指令中的逻辑地址被映射到具有比逻辑地址大的地址空间的物理地址。非故障字的地址映射到较大地址空间中与逻辑地址相同的字。指向故障字的逻辑地址映射到位于较大地址空间中但不在逻辑地址的地址空间中的冗余字。由于在访问时间内向寄存器文件解码器提供的所有地址指向非故障字，因此在访问时间期间不需要与地址比较相关联的延迟代价。

8. 发明授权

US06868489B2 Carry generation in address calculation 失效
标题翻译：在地址计算中进行生成
公开(公告)号：US06868489B2
公开(公告)日：2005-03-15
申请号：US10038958
申请日：2002-01-02
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F7/50 , G06F7/505 , G06F9/355 , G06F12/00
CPC分类号： G06F7/5055 , G06F7/508 , G06F9/355
摘要： Embodiments are provided in which the generation of a carry of a sum of two numbers can be implemented by adding only some most significant bits of the two numbers and assuming that the sum of the remaining bits do not generate a carry. Other embodiments are also provided in which the generation of the carry of a sum of the two numbers can be implemented using carry look-ahead techniques wherein generate and propagate terms are generated. By combining the product terms of the carry function and combining pairs of propagate or generate terms, the generation of the carry of the sum of the two numbers can be implemented in an And-Or-Inverter function less complex than that of prior art. Still other embodiments are provided in which one operand of a carry generation circuit comes from a fixed source and the other operand is selected from several forwarding sources. As a result, the selection of the operands and the generation of the propagate and generate terms for generating the carry can be implemented in a single complex domino level of logic which includes a sum of product followed by a simple two-way gate.
摘要翻译：提供了这样的实施例，其中可以通过仅添加两个数字的一些最高有效位并且假设剩余位的和不产生进位来实现两个数的和的进位的产生。还提供了其他实施例，其中可以使用生成和传播术语的携带预先技术来实现两个数字的和的进位的生成。通过组合进位函数的乘积项和组合传播或生成项对，可以以比现有技术更复杂的并 - 或 - 反相器功能来实现两个数的和的进位的产生。还提供了其他实施例，其中进位发生电路的一个操作数来自固定源，另一个操作数从多个转发源中选择。结果，操作数的选择以及用于生成进位的传播和产生条件的产生可以在单个复杂的多米诺骨牌级逻辑中实现，该逻辑包括产品的和之后是简单的双向门。

9. 发明授权

US5793944A System for restoring register data in a pipelined data processing system using register file save/restore mechanism 失效
标题翻译：用于使用寄存器文件保存/恢复机制在流水线数据处理系统中恢复寄存器数据的系统
公开(公告)号：US5793944A
公开(公告)日：1998-08-11
申请号：US718040
申请日：1996-09-13
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F9/30 , G06F9/38 , G06F11/00
CPC分类号： G06F9/30116 , G06F9/30141 , G06F9/3863
摘要： Systems are provided for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition. One embodiment concerns a latch feedback assembly, such as a SRL, which includes multiple series-connected latches having a feedback connection between last and first latches. The latches are clocked to temporarily reserve a delayed backup copy of data from the first latch on the last latch. Upon detection of an exception, the backup copy is first preserved by disabling writes to the last latch; then the backup copy is copied to the first latch to restore the first latch to its state prior to occurrence of the exception. Another embodiment involves a register file save/restore mechanism, in which an additional bank of registers, called a "backup register", is coupled to a register file. When data is stored in an address of the register file, the address and its data content are also stored in the backup register. One portion of the backup contains the address, and another portion contains the data. If an exception occurs after data is stored in the register file, the register file may contain incorrect data. However, the backup contains a copy of "correct" data previously stored in the register file. Thus, the register file may returned to its state prior to the exception by copying the correct data from the backup register to the register file.
摘要翻译：系统被提供用于在流水线数据处理系统中保存寄存器数据，并且在异常情况下将数据恢复到适当的寄存器。一个实施例涉及一种闩锁反馈组件，例如SRL，其包括具有在最后和第一锁存器之间的反馈连接的多个串联连接的锁存器。锁存器被计时以临时保留来自最后一个锁存器上的第一个锁存器的数据的延迟备份副本。检测到异常后，首先通过禁止对最后一个锁存器的写入来保留备份副本; 那么将备份副本复制到第一个锁存器，以便在出现异常之前将第一个锁存器恢复到其状态。另一个实施例涉及一种寄存器文件保存/恢复机制，其中称为“备份寄存器”的附加寄存器组耦合到寄存器文件。当数据存储在寄存器文件的地址中时，地址及其数据内容也存储在备份寄存器中。备份的一部分包含地址，另一部分包含数据。如果数据存储在寄存器文件中发生异常，则寄存器文件可能包含不正确的数据。但是，备份包含之前存储在寄存器文件中的“正确”数据的副本。因此，寄存器文件可能会在异常之前通过将备份寄存器中的正确数据复制到寄存器文件中而返回到其状态。

10. 发明授权

US5644780A Multiple port high speed register file with interleaved write ports for use with very long instruction word (vlin) and n-way superscaler processors 失效
标题翻译：具有交错写入端口的多端口高速寄存器文件，用于使用非常长的指令字（vlin）和n路超标量处理器
公开(公告)号：US5644780A
公开(公告)日：1997-07-01
申请号：US459490
申请日：1995-06-02
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38 , G06F12/08 , G06F12/04 , G06F12/06
CPC分类号： G06F9/30141 , G06F9/3012 , G06F9/3885
摘要： A high speed register file is provided for use with Very Long Word Instruction (VLIW) and N-way superscaler processors. The high speed register file includes a selected number of copies of a general purpose register (GPR) building block. The GPR building block includes at least two interleaved sub-banks of registers. Each of the sub-banks includes a number N of write ports and a number M of read ports. The sub-banks are interleaved by write ports and have non-interleaved read ports.
摘要翻译：提供了一个高速寄存器文件，用于使用超长字指令（VLIW）和N路超标量处理器。高速寄存器文件包括通用寄存器（GPR）构建块的选定份数。 GPR构建块至少包括两个交错子寄存器。每个子行包括N个写入端口和M个读取端口。子行通过写入端口进行交织，并具有非交错的读取端口。

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