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21. 发明授权

US08281214B2 Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel 有权
标题翻译：用于读通道的可编程准循环低密度奇偶校验（QC LDPC）编码器
公开(公告)号：US08281214B2
公开(公告)日：2012-10-02
申请号：US12288221
申请日：2008-10-17
申请人： Shaohua Yang , Changyou Xu , Richard Rauschmayer , Hao Zhong , Weijun Tan
发明人： Shaohua Yang , Changyou Xu , Richard Rauschmayer , Hao Zhong , Weijun Tan
IPC分类号： H03M13/00
CPC分类号： H03M13/05 , G06F11/1008 , H03M13/116 , H03M13/2792
摘要： The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.
摘要翻译：本发明是用于编码用户数据的可编程QC LDPC编码器。编码器可以被配置为用读通道实现。编码器可以包括多个桶形移位器电路。桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。桶形移位器电路还被配置为输出奇偶校验位。编码器还可以包括编码器交织器存储器。编码器交织器存储器可以与桶形移位器电路通信耦合，并且可以接收从桶形移位器电路输出的奇偶校验位。编码器交织器可以被配置为交织奇偶校验位。此外，编码器可以被配置为将交错的奇偶校验位输出到多路复用器。桶形移位器电路可以通过编码算法生成多个奇偶校验位：p = u * GT。

22. 发明授权

US08223827B2 Method and apparatus for generating filter tap weights and biases for signal dependent branch metric computation 失效
标题翻译：用于产生滤波器抽头权重和偏置的方法和装置，用于信号相关分支度量计算
公开(公告)号：US08223827B2
公开(公告)日：2012-07-17
申请号：US10839784
申请日：2004-05-05
申请人： Jonathan James Ashley , Keenan Terrell O'Brien , Richard Rauschmayer , Sumeet Sanghvi , Anne Q. Ye , Kaichi Zhang
发明人： Jonathan James Ashley , Keenan Terrell O'Brien , Richard Rauschmayer , Sumeet Sanghvi , Anne Q. Ye , Kaichi Zhang
IPC分类号： H03K5/159
CPC分类号： H03H17/0294
摘要： A method and apparatus are provided for determining a plurality of filter tap weights or biases (or both) for a noise predictive filter used to generate one or more signal dependent branch metrics. A filter tap weight or filter bias (or both) are adaptively accumulated for each possible data condition. The data conditions may comprise, for example, each possible data pattern for a given data dependency length. The appropriate accumulated filter tap weight or bias to update can be selected based on a data condition associated with the current received data. The filter tap weights associated with a delay 0 tap can be adapted for each filter condition except for a single normalizing condition, whose corresponding delay 0 tap remains fixed.
摘要翻译：提供了一种用于确定用于生成一个或多个信号相关分支量度的噪声预测滤波器的多个滤波器抽头权重或偏差（或两者）的方法和装置。对于每个可能的数据条件，自适应地累积滤波器抽头权重或滤波器偏置（或两者）。数据条件可以包括例如给定数据依赖性长度的每个可能的数据模式。可以基于与当前接收到的数据相关联的数据条件来选择适当的累积滤波器抽头权重或要更新的偏置。与延迟0抽头相关联的滤波器抽头权重可以适用于每个滤波器条件，除了单个归一化条件，其相应的延迟0抽头保持固定。

23. 发明授权

US08149527B2 Systems and methods for reducing attenuation of information derived from a defective medium 有权
标题翻译：用于减少从有缺陷介质得到的信息衰减的系统和方法
公开(公告)号：US08149527B2
公开(公告)日：2012-04-03
申请号：US12111889
申请日：2008-04-29
申请人： Weijun Tan , Hao Zhong , Yuan Xing Lee , Richard Rauschmayer , Shaohua Yang , Harley Burger , Kelly Fitzpatrick , Changyou Xu
发明人： Weijun Tan , Hao Zhong , Yuan Xing Lee , Richard Rauschmayer , Shaohua Yang , Harley Burger , Kelly Fitzpatrick , Changyou Xu
IPC分类号： G11B5/02 , G11B27/36 , G11B5/09
CPC分类号： G11B20/18 , G11B20/10009 , G11B20/10287 , G11B20/10296 , H03M13/3905 , H03M13/3961 , H03M13/4146 , H03M13/6343 , H03M13/658
摘要： Various embodiments of the present invention provide systems and methods for data regeneration. For example, a method for data regeneration is disclosed that includes receiving a data input derived from a medium, determining a media defect corresponding to the data input, and determining an attenuation factor associated with the defective medium. Based at least in part on the determination that the medium is defective, amplifying the data input by a derivative of the attenuation factor to regenerate the data.
摘要翻译：本发明的各种实施例提供了用于数据再生的系统和方法。例如，公开了一种用于数据再生的方法，包括接收从介质导出的数据输入，确定与数据输入相对应的介质缺陷，以及确定与缺陷介质相关联的衰减因子。至少部分地基于介质有缺陷的确定，通过衰减因子的导数来放大输入的数据以再生数据。

24. 发明申请

US20110080211A1 Systems and Methods for Noise Reduced Data Detection 审中-公开
标题翻译：降噪数据检测系统和方法
公开(公告)号：US20110080211A1
公开(公告)日：2011-04-07
申请号：US12992948
申请日：2009-04-17
申请人： Shaohua Yang , Yuan Xing Lee , Richard Rauschmayer , Hongwei Song , Jingfeng Liu , Weijun Tan
发明人： Shaohua Yang , Yuan Xing Lee , Richard Rauschmayer , Hongwei Song , Jingfeng Liu , Weijun Tan
IPC分类号： H03K5/00
CPC分类号： G11B20/24 , G11B20/10037 , G11B20/10194 , G11B20/10527 , G11B20/1833 , G11B20/1879 , G11B2020/1062 , G11B2020/10685 , G11B2020/10694 , G11B2020/10759 , G11B2020/183 , G11B2020/185 , G11B2220/2516 , H03M13/1105 , H03M13/2948 , H03M13/3746 , H03M13/6343 , H04L1/005 , H04L1/0057
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide noise reduced data processing circuits. Such circuits include a selector circuit, a sample set averaging circuit, and a data detection circuit. The selector circuit provides either a new sample set or an averaged sample set as a sample output based on a select control signal. The sample set averaging circuit receives the new sample set and provides the averaged sample set. The averaged sample set is based upon two or more instances of the new sample set. The data detection circuit receives the sample output, and performs a data detection algorithm on the sample output and provides the select control signal and a data output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，本发明的一些实施例提供降噪数据处理电路。这种电路包括选择器电路，采样组平均电路和数据检测电路。选择器电路基于选择控制信号提供新的采样集或平均采样集作为采样输出。样本集平均电路接收新的样本集并提供平均的样本集。平均采样集基于新样本集的两个或多个实例。数据检测电路接收采样输出，对采样输出执行数据检测算法，提供选择控制信号和数据输出。

25. 发明申请

US20110058631A1 Systems and Methods for Enhanced Flaw Scan in a Data Processing Device 有权
标题翻译：数据处理设备中增强型扫描扫描的系统和方法
公开(公告)号：US20110058631A1
公开(公告)日：2011-03-10
申请号：US12556180
申请日：2009-09-09
申请人： Weijun Tan , Shaohua Yang , Hongwei Song , Richard Rauschmayer
发明人： Weijun Tan , Shaohua Yang , Hongwei Song , Richard Rauschmayer
IPC分类号： H04L27/00
CPC分类号： H04L1/0057 , H04L1/0045
摘要： Various embodiments of the present invention provide systems and methods for flaw scan in a data processing system. As one example, a data processing system is disclosed that includes a data detector circuit, a bit sign inverting circuit, and an LDPC decoder circuit. The data detector circuit receives a verification data set that is an invalid LDPC codeword, and applies a data detection algorithm to the verification data set to yield a detected output. The bit sign inverting circuit modifies the sign of one or more elements of a first derivative of the detected output to yield a second derivative of the detected output. The second derivative of the detected output is an expected valid LDPC codeword. The LDPC decoder circuit applies a decoding algorithm to the second derivative of the detected output to yield a decoded output.
摘要翻译：本发明的各种实施例提供了在数据处理系统中的缺陷扫描的系统和方法。作为一个示例，公开了包括数据检测器电路，位符号反相电路和LDPC解码器电路的数据处理系统。数据检测器电路接收作为无效LDPC码字的验证数据集，并将数据检测算法应用于验证数据集以产生检测到的输出。位符号反相电路修改检测输出的一阶导数的一个或多个元素的符号，以产生检测到的输出的二阶导数。所检测的输出的二阶导数是期望的有效LDPC码字。 LDPC解码器电路将解码算法应用于检测输出的二阶导数，以产生解码输出。

26. 发明申请

US20100322048A1 Systems and Methods for Codec Usage Control During Storage Pre-read 有权
标题翻译：存储预读期间编码器使用控制的系统和方法
公开(公告)号：US20100322048A1
公开(公告)日：2010-12-23
申请号：US12487638
申请日：2009-06-18
申请人： Shaohua Yang , Yuan Xing Lee , Changyou Xu , Richard Rauschmayer , Harley Burger , Kapil Gaba
发明人： Shaohua Yang , Yuan Xing Lee , Changyou Xu , Richard Rauschmayer , Harley Burger , Kapil Gaba
IPC分类号： G11B20/00
CPC分类号： G11B20/10527 , G11B20/10194 , G11B2020/10694 , G11B2020/10805 , G11B2220/2516 , H03M13/1102 , H03M13/2957 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an increased iteration enable signal, a first detector circuit, a second detector circuit, and a data decoding circuit. The first detector circuit receives a data set and performs a data detection on the data set to provide a detected data set. The data decoding circuit receives a derivative of the detected data set and performs a decoding process to provide a decoded data set. The decoded data set is provided to the second detector circuit based at least in part on an assertion level of the increased iteration enable signal.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种数据处理电路，其包括增加的迭代使能信号，第一检测器电路，第二检测器电路和数据解码电路。第一检测器电路接收数据组并对数据集执行数据检测以提供检测数据集。数据解码电路接收检测数据组的导数，并进行解码处理，提供解码数据组。解码数据集至少部分地基于增加的迭代使能信号的断言电平被提供给第二检测器电路。

27. 发明申请

US20100218020A1 Systems and Methods for Operational Power Management 有权
标题翻译：操作电源管理系统与方法
公开(公告)号：US20100218020A1
公开(公告)日：2010-08-26
申请号：US12772108
申请日：2010-04-30
申请人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
发明人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
IPC分类号： G06F1/26 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/04 , G06F1/24 , G06F1/3268 , Y02D10/154
摘要： Various systems and methods for power management are disclosed herein. For example, a synchronous semiconductor circuit is disclosed that includes two or more clock sources and a power management controller. The power management controller is operable to apply power to one of the clock sources and to select another of the clock sources for synchronization of the circuit. Then, upon stabilization of the first clock source, it is selected by the power management controller to synchronize the circuit.
摘要翻译：本文公开了用于电力管理的各种系统和方法。例如，公开了包括两个或更多个时钟源和电源管理控制器的同步半导体电路。功率管理控制器可操作以将功率施加到其中一个时钟源并选择另一个时钟源以用于该电路的同步。然后，在稳定第一时钟源时，由电源管理控制器选择电路同步。

28. 发明申请

US20100208377A1 Systems and Methods for Inter-Location Control of Storage Access 有权
标题翻译：存储访问的位置间控制的系统和方法
公开(公告)号：US20100208377A1
公开(公告)日：2010-08-19
申请号：US12527311
申请日：2007-10-30
申请人： Jeffrey P. Grundvig , Richard Rauschmayer , Timothy T. Ding
发明人： Jeffrey P. Grundvig , Richard Rauschmayer , Timothy T. Ding
IPC分类号： G11B5/09
CPC分类号： G11B5/09 , G11B20/10 , G11B20/10222 , G11B2020/1267 , G11B2020/1281 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for controlling access to a magnetic storage medium. As one example, a method for controlling access to a magnetic storage medium is disclosed that includes providing a location count indicating a location between a portion of a first servo data sector of a magnetic storage media and a portion of a second servo data sector of the magnetic storage media, and asserting an enable window signal based upon the location count.
摘要翻译：本发明的各种实施例提供了用于控制对磁存储介质的访问的系统和方法。作为一个示例，公开了一种用于控制对磁存储介质的访问的方法，其包括提供指示磁存储介质的第一伺服数据扇区的一部分与第二伺服数据扇区的部分之间的位置的位置计数磁存储介质，并且基于位置计数来确定使能窗口信号。

29. 发明申请

US20070064836A1 Format efficient timing acquisition for magnetic recording read channels 有权
标题翻译：为磁记录读通道格式化高效的定时采集
公开(公告)号：US20070064836A1
公开(公告)日：2007-03-22
申请号：US11228762
申请日：2005-09-16
申请人： Jason Byrne , German Feyh , Jeffrey Grundvig , Aravind Nayak , Richard Rauschmayer
发明人： Jason Byrne , German Feyh , Jeffrey Grundvig , Aravind Nayak , Richard Rauschmayer
IPC分类号： H04L27/00 , H03D3/24 , H04L7/00
CPC分类号： H04L7/0054 , H04L7/0004 , H04L2007/047
摘要： A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.
摘要翻译：一种使用前置码同步位的磁记录应用的定时恢复电路。定时恢复电路使用具有数字旋转器的经修改的数字锁相环。模数转换器（ADC）接收模拟输入，并向数字旋转器提供ADC数字采样。为了补偿模拟延迟和回转，应注意，改变ADC中的采样点等同于在输出中引入相位变化。例如，使用数字旋转器可以比通过改变模拟采样点更快地数字地引入该相位变化。与改变ADC采样点所需的时间相比，数字旋转器几乎瞬间捕捉到初始相位估计。当ADC转换到初始相位估计时，数字旋转器将逐步退化，直到ADC达到初始相位估计。

30. 发明授权

US08468418B2 Systems and methods for queue based data detection and decoding 有权
标题翻译：基于队列的数据检测和解码的系统和方法
公开(公告)号：US08468418B2
公开(公告)日：2013-06-18
申请号：US13547940
申请日：2012-07-12
申请人： Shaohua Yang , Hao Zhong , Weijun Tan , Richard Rauschmayer , Yuan Xing Lee
发明人： Shaohua Yang , Hao Zhong , Weijun Tan , Richard Rauschmayer , Yuan Xing Lee
IPC分类号： H03M13/00 , H03M13/03
CPC分类号： H03M13/2987 , G11B20/18 , G11B2020/185 , G11B2220/2516 , H03M13/09 , H03M13/1102 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/27 , H03M13/3905 , H03M13/4146 , H03M13/6331 , H03M13/6337 , H04L1/005 , H04L1/0057 , H04L1/0065
摘要： Various embodiments of the present invention provide systems and methods for variable iteration data processing.
摘要翻译：本发明的各种实施例提供了用于可变迭代数据处理的系统和方法。

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