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21. 发明申请

US20150147992A1 INTEGRATED RECEIVER AND INTEGRATED CIRCUIT HAVING INTEGRATED INDUCTORS AND METHOD THEREFOR 有权
标题翻译：具有集成电感器的集成接收器和集成电路及其方法
公开(公告)号：US20150147992A1
公开(公告)日：2015-05-28
申请号：US14612346
申请日：2015-02-03
申请人： Silicon Laboratories Inc.
发明人： Ramin Khoini-Poorfard , Alessandro Piovaccari , Aslamali A. Rafi , Mustafa H. Koroglu , David S. Trager , Abdulkerim L. Coban
IPC分类号： H04B1/28 , H04L27/148
CPC分类号： H04B1/28 , H03H11/04 , H04B1/30 , H04L27/148 , H04N5/455 , H04N5/50
摘要： In one form, an integrated receiver includes a tracking bandpass filter, a tunable lowpass filter, and a mixer formed on a single integrated circuit chip. The tracking bandpass filter has an input for receiving a radio frequency (RF) input signal, and an output, and comprises a variable capacitor having a capacitance that varies in response to a bandpass frequency control signal, in parallel with an integrated inductor. The integrated inductor comprises a plurality of windings formed in a plurality of metal layers. The tunable lowpass filter has an input coupled to the output of the tracking bandpass filter, and an output and having a tuning input for receiving a cutoff frequency signal. The mixer has a signal input coupled to the output of the tunable lowpass filter, a local oscillator input for receiving a local oscillator signal, and a signal output for providing a converted RF signal.
摘要翻译：在一种形式中，集成接收器包括跟踪带通滤波器，可调谐低通滤波器和形成在单个集成电路芯片上的混频器。跟踪带通滤波器具有用于接收射频（RF）输入信号和输出的输入，并且包括与集成电感器并联的具有响应于带通频率控制信号而变化的电容的可变电容器。集成电感器包括形成在多个金属层中的多个绕组。可调谐低通滤波器具有耦合到跟踪带通滤波器的输出的输入端和输出端，并具有用于接收截止频率信号的调谐输入端。混频器具有耦合到可调谐低通滤波器的输出的信号输入，用于接收本地振荡器信号的本地振荡器输入和用于提供经转换的RF信号的信号输出。

22. 发明授权

US08885106B2 Multi-tuner using interpolative dividers 有权
标题翻译：多调谐器使用内插分频器
公开(公告)号：US08885106B2
公开(公告)日：2014-11-11
申请号：US13799384
申请日：2013-03-13
申请人： Silicon Laboratories Inc.
发明人： Mustafa H. Koroglu , Abdulkerim L. Coban
IPC分类号： H04N5/44 , H04N5/50 , H04N5/46
CPC分类号： H04N5/4401 , H04N5/455 , H04N5/50 , H04N21/4263 , H04N21/4382
摘要： An apparatus includes a splitter to receive a radio frequency (RF) signal and to provide the RF signal to multiple channels of a tuner. Each channel may include an amplifier to amplify the RF signal, a mixer to downconvert the amplified RF signal to a second frequency signal using a local oscillator (LO) signal, where each of the channels is configured to receive a different LO signal, a filter to filter the downconverted second frequency signal, and a digitizer to digitize the downconverted second frequency signal. A clock generation circuit has multiple interpolative dividers and a frequency synthesizer to generate a reference clock signal. Each of the interpolative dividers is configured to receive the reference clock signal, generate a corresponding LO signal, and provide the corresponding LO signal to the mixer of at least one of the channels.
摘要翻译：一种装置包括用于接收射频（RF）信号并将RF信号提供给调谐器的多个信道的分离器。每个通道可以包括用于放大RF信号的放大器，使用本地振荡器（LO）信号将放大的RF信号下变频到第二频率信号的混频器，其中每个信道被配置为接收不同的LO信号，滤波器对下变频的第二频率信号进行滤波，以及数字转换器，对下变频的第二频率信号进行数字化。时钟发生电路具有多个内插分频器和频率合成器，以产生参考时钟信号。每个内插分频器被配置为接收参考时钟信号，产生相应的LO信号，并将相应的LO信号提供给至少一个信道的混频器。

23. 发明申请

US20140226074A1 CONFIGURABLE BUFFER FOR AN INTEGRATED CIRCUIT 有权
标题翻译：用于集成电路的可配置缓冲器
公开(公告)号：US20140226074A1
公开(公告)日：2014-08-14
申请号：US14254340
申请日：2014-04-16
申请人： SILICON LABORATORIES INC.
发明人： András Vince Horvath , Abdulkerim L. Coban , Pio Balmelli , Ramin Khoini-Poorfard , Alessandro Piovaccari
IPC分类号： H04N5/50 , H03J5/24
CPC分类号： H04N5/50 , H03J5/24 , H04L25/0292 , H04N5/165 , H04N5/455 , H04N21/42607
摘要： In one embodiment, an internal buffer may be provided within an integrated circuit (IC) to convert a signal to an output current to be output via a pin of the IC, under control of a switch which can be controlled based on a configuration setting of the IC, and may selectively directly couple the signal to the pin when the IC is coupled to an external driver circuit.
摘要翻译：在一个实施例中，内部缓冲器可以设置在集成电路（IC）内，以在开关的控制下将信号转换成经由IC的引脚输出的输出电流，该开关可以基于配置设置 IC，并且当IC耦合到外部驱动器电路时，可以选择性地将信号耦合到引脚。

24. 发明授权

US10931300B1 Low-power programmable bandwidth continuous-time delta sigma modulator based analog to digital converter 有权
公开(公告)号：US10931300B1
公开(公告)日：2021-02-23
申请号：US16588113
申请日：2019-09-30
申请人： Silicon Laboratories Inc.
发明人： Abdulkerim L. Coban , Sanjeev Suresh
IPC分类号： H03M3/00 , H03F3/45 , H04B1/00
摘要： A continuous-time (CT) delta-sigma modulator (DSM) based analog to digital converter (ADC) in a radio receive chain supports a wide range of data rates in a power efficient way in a small die area. The ADC utilizes a 2nd order loop-filter with a single-amplifier loop-filter topology using a two stage Miller amplifier with a feed forward path and a push-pull output stage. High bandwidth operations utilize a “negative-R” compensation scheme at the amplifier input. Negative-R assistance is disabled for low data rate applications. With the negative-R assistance disabled, loop-filter resistor values are increased, instead of only the loop filter capacitor values to scale the noise transfer function (NTF), thereby limiting the capacitor area needed and enabling lower power operation. The NTF zero location is programmable allowing the NTF zero to be located near the intermediate frequency for different bandwidths to reduce the DSM quantization noise contribution for narrow-band (low data rate) applications.

25. 发明授权

US10826501B1 Ring oscillator based RC calibration circuit 有权
公开(公告)号：US10826501B1
公开(公告)日：2020-11-03
申请号：US16450083
申请日：2019-06-24
申请人： Silicon Laboratories Inc.
发明人： Abdulkerim L. Coban , Wenhuan Yu , Mustafa H. Koroglu
IPC分类号： H03L7/08 , H03K21/00 , H03K3/03 , H03L7/099 , H03H11/04 , H03H11/12
摘要： A calibration operation adjusts a frequency of a ring oscillator to a desired frequency by adjusting programmable RC circuits in the stages of the ring oscillator. The programmable RC circuits have programmable capacitors, resistors, or both. The RC circuits account for most of the delay through the ring oscillator. Another circuit with its own RC time constant is calibrated based on the adjustments made to the RC circuits in the ring oscillator to achieve the desired frequency.

26. 发明授权

US10523251B1 Automatic gain control system and method with improved blocker performance 有权
公开(公告)号：US10523251B1
公开(公告)日：2019-12-31
申请号：US16156294
申请日：2018-10-10
申请人： SILICON LABORATORIES INC.
发明人： Abdulkerim L. Coban , Emmanuel Gautier , Fabrice Portier , Pascal Blouin , Wenhuan Yu
IPC分类号： H04B1/10 , H04L25/08 , H04B17/336 , H03F3/19 , H03G3/30 , H04L25/03
摘要： A communications receiver with improved blocker performance including multiple gain tables selected based on a number of reductions or back offs from a maximum coarse gain setting. A receiver chain with multiple gain stages converts a received signal to a digital format, determines the power level of the received signal, and provides an overload indication. A first gain table maximizes SNR and SNDR for weak blockers and at least one additional gain table successively improves SNDR for stronger blockers. An AGC circuit initially sets the coarse gain setting to maximum, and backs off a number of coarse gain steps until the receiver chain is not overloaded. The number of back off steps is used to select a gain table, the power level is used to select an entry in the selected table, and the selected entry includes gain settings for the gain stages of the receiver chain.

27. 发明授权

US09729162B1 Flexible signal chain processing circuits and method 有权
公开(公告)号：US09729162B1
公开(公告)日：2017-08-08
申请号：US15223310
申请日：2016-07-29
申请人： SILICON LABORATORIES INC.
发明人： Wenhuan Yu , Abdulkerim L. Coban
IPC分类号： H03M1/06 , H03F3/45 , H03K5/1252 , H03M1/12 , H03H11/04 , H03M1/00
CPC分类号： H03M1/0617 , H03F3/45183 , H03F3/45475 , H03F3/45636 , H03F3/45659 , H03F2200/267 , H03F2203/45022 , H03F2203/45222 , H03F2203/45418 , H03F2203/45424 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528 , H03F2203/45591 , H03H11/04 , H03H11/0422 , H03H11/1213 , H03K5/1252 , H03M1/00 , H03M1/12 , H03M1/145 , H03M1/502
摘要： In one form, a signal chain circuit includes a signal chain processing circuit between an input for receiving a differential input signal having a first common-mode voltage, and an output for providing a differential output signal having a second, different common-mode voltage. It includes an amplifier with a differential output stage coupled to a differential input stage and having positive and negative output terminals forming its output, and positive and negative feedback terminals. The differential output stage provides a first voltage drop between the positive output terminal and the positive feedback terminal, and a second voltage drop between the negative output terminal and the negative feedback terminal. The common-mode feedback circuit regulates a common-mode voltage between the positive and negative feedback terminals to the second common-mode voltage. In another form, an analog-to-digital converter includes a range extending logic circuit to extend the range of a ring oscillator based analog-to-digital converter.

28. 发明授权

US09094042B2 DAC current source matrix patterns with gradient error cancellation 有权
标题翻译： DAC电流源矩阵模式与梯度误差消除
公开(公告)号：US09094042B2
公开(公告)日：2015-07-28
申请号：US13963788
申请日：2013-08-09
申请人： Silicon Laboratories Inc.
发明人： Péter Onódy , Abdulkerim L. Coban
IPC分类号： H03M1/66
CPC分类号： H03M1/66 , H03M1/0648 , H03M1/687 , H03M1/745 , H03M1/747
摘要： First order gradient errors are canceled with no current source splitting by placing consecutive current sources symmetrically around the center of the array. Consecutive elements that correspond to small input amplitudes (mid-scale codes) make a smaller spatial jump than those correspond to larger signal amplitudes. Both linear and second order gradients are reduced by splitting each current cell into two and placing sub-elements symmetrically with respect to the center of the array to address the linear gradient effect. To address second order gradients, current element placement follows a pattern such that consecutive element pairs are chosen with one of the pair being placed with respect to the zero error contour of the second order gradient so as to have a positive error and the second of the pair being placed so as to have a negative error resulting in reduced second order error accumulation.
摘要翻译：通过将连续的电流源对称地围绕阵列的中心来消除第一阶梯度误差，没有电流源分裂。对应于小输入幅度（中等尺度代码）的连续元件比对应于较大信号幅度的空间跳跃小。通过将每个当前单元分成两个并将子元素相对于阵列的中心对称放置以解决线性梯度效应，可以减少线性和二阶梯度。为了解决二阶梯度，当前元素放置遵循模式，使得连续的元素对被选择，其中一对中的一个相对于二阶梯度的零误差轮廓被放置，以便具有正的误差，而第二个对被放置成具有导致减少的二阶误差累积的负误差。

29. 发明授权

US08983419B2 Integrated receiver and integrated circuit having integrated inductors and method therefor 有权
标题翻译：具有集成电感器的集成接收器和集成电路及其方法
公开(公告)号：US08983419B2
公开(公告)日：2015-03-17
申请号：US14195064
申请日：2014-03-03
申请人： Silicon Laboratories Inc.
发明人： Ramin Khoini-Poorfard , Alessandro Piovaccari , Aslamali A. Rafi , Mustafa H. Koroglu , David S. Trager , Abdulkerim L. Coban
IPC分类号： H04B1/06 , H04N5/50 , H04B1/30 , H04B1/28 , H03H11/04 , H04N5/455
CPC分类号： H04B1/28 , H03H11/04 , H04B1/30 , H04L27/148 , H04N5/455 , H04N5/50
摘要： An integrated receiver includes a first signal processing path, a second signal processing path, and a controller. The first signal processing path has an input and an output for providing a first processed signal, and comprises a first tracking bandpass filter having a first integrated inductor formed with windings in a first number of metal layers of the integrated receiver. The second signal processing path has an input and an output for providing a second processed signal, and comprises a second tracking bandpass filter having a second integrated inductor formed with windings in a second number of metal layers of the integrated receiver. The second number of windings is lower than the first number. The controller enables one of the first and second signal processing paths corresponding to a selected channel of a radio frequency (RF) input signal to provide an output signal.
摘要翻译：集成接收机包括第一信号处理路径，第二信号处理路径和控制器。第一信号处理路径具有用于提供第一处理信号的输入和输出，并且包括第一跟踪带通滤波器，该第一跟踪带通滤波器具有由集成接收器的第一数量的金属层中的绕组形成的第一集成电感器。第二信号处理路径具有用于提供第二处理信号的输入和输出，并且包括第二跟踪带通滤波器，该第二跟踪带通滤波器具有形成有集成接收器的第二数量金属层中的绕组的第二集成电感器。第二个绕组数量低于第一个数量。控制器使得与射频（RF）输入信号的所选频道相对应的第一和第二信号处理路径之一提供输出信号。

30. 发明申请

US20150042498A1 DAC CURRENT SOURCE MATRIX PATTERNS WITH GRADIENT ERROR CANCELLATION 有权
标题翻译： DAC电流源矩阵与梯度误差消除
公开(公告)号：US20150042498A1
公开(公告)日：2015-02-12
申请号：US13963788
申请日：2013-08-09
申请人： Silicon Laboratories Inc.
发明人： Peter Onody , Abdulkerim L. Coban
IPC分类号： H03M1/66
CPC分类号： H03M1/66 , H03M1/0648 , H03M1/687 , H03M1/745 , H03M1/747
摘要： First order gradient errors are canceled with no current source splitting by placing consecutive current sources symmetrically around the center of the array. Consecutive elements that correspond to small input amplitudes (mid-scale codes) make a smaller spatial jump than those correspond to larger signal amplitudes. Both linear and second order gradients are reduced by splitting each current cell into two and placing sub-elements symmetrically with respect to the center of the array to address the linear gradient effect. To address second order gradients, current element placement follows a pattern such that consecutive element pairs are chosen with one of the pair being placed with respect to the zero error contour of the second order gradient so as to have a positive error and the second of the pair being placed so as to have a negative error resulting in reduced second order error accumulation.
摘要翻译：通过将连续的电流源对称地围绕阵列的中心来消除第一阶梯度误差，没有电流源分裂。对应于小输入幅度（中等尺度代码）的连续元件比对应于较大信号幅度的空间跳跃小。通过将每个当前单元分成两个并将子元素相对于阵列的中心对称放置以解决线性梯度效应，可以减少线性和二阶梯度。为了解决二阶梯度，当前元素放置遵循模式，使得连续的元素对被选择，其中一对中的一个相对于二阶梯度的零误差轮廓被放置，以便具有正的误差，而第二个对被放置成具有导致减少的二阶误差累积的负误差。

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