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1. 发明授权

US11671109B2 Constant current digital to analog converter systems and methods 有权
公开(公告)号：US11671109B2
公开(公告)日：2023-06-06
申请号：US16740184
申请日：2020-01-10
申请人： Apple Inc.
发明人： Toshitsugu Kawashima , Jose Antonio Gómez Urdampilleta , Masahiro Takeuchi , Yohei Ishizone , Ryo Endo
IPC分类号： H03M1/78 , H03M1/80 , H03M1/08 , H03M1/68
CPC分类号： H03M1/808 , H03M1/08 , H03M1/687
摘要： An electronic device may include a digital to analog converter receiving digital signals and outputting analog signals based on the received digital signals. The electronic device may also include a power source to supply current to the digital to analog converter. The digital to analog converter may include a first resistor ladder section to electrically couple an output node of the digital to analog converter to the power source via a first number of resistors in series. The digital to analog converter may also include a second resistor ladder section to electrically couple the output node to a reference voltage via a second number of resistors in series. The sum of the first number of resistors in series and the second number of resistors in series may be the same for each of the different analog signals.

2. 发明授权

US10014874B1 System and method of minimizing differential non-linearity (DNL) for high resolution current steering DAC 有权
公开(公告)号：US10014874B1
公开(公告)日：2018-07-03
申请号：US15792563
申请日：2017-10-24
申请人： Yuan-Ju Chao , Ta-Shun Chu
发明人： Yuan-Ju Chao , Ta-Shun Chu
IPC分类号： H03M1/66 , H03M1/06 , H03M1/68
CPC分类号： H03M1/0612 , H03M1/662 , H03M1/687 , H03M1/742
摘要： A current steering converter fabricated using a predetermined integrated circuit technology includes a unary portion having one or more current sources and a binary portion including a plurality of switches controlled by a decoder, the switches coupled to a converter output; and a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length of the device and M is an integer representing multiple number.

3. 发明授权

US09178524B1 Hybrid R-2R structure for low glitch noise segmented DAC 有权
标题翻译：用于低毛刺噪声分段DAC的混合R-2R结构
公开(公告)号：US09178524B1
公开(公告)日：2015-11-03
申请号：US14493254
申请日：2014-09-22
申请人： QUALCOMM Incorporated
发明人： Sang Min Lee , Dongwon Seo
IPC分类号： H03M1/66 , H03M1/08 , H03M1/68 , H03M1/78
CPC分类号： H03M1/0863 , H03M1/0612 , H03M1/0881 , H03M1/687 , H03M1/785
摘要： The apparatus may be an N-bit DAC including (2M−1) parallel stages associated with M most significant bits, and (N-M) stages associated with (N-M) least significant bits. The (2M−1) parallel stages may deliver a first current to current-summing nodes of the DAC. The (N-M) stages may include a resistive network and a second pair of switches, and may deliver a second current to the resistive network of the stage. Each resistive network may scale the respectively delivered currents according to a binary weight of a stage corresponding to the resistive network, and may deliver the scaled currents to the pair of current-summing nodes. At least one of the (N-M) stages may be separated from the remaining stages.
摘要翻译：该装置可以是包括与M个最高有效位相关联的（2M-1）个并行级和与（N-M）个最低有效位相关联的（N-M）级的N位DAC。（2M-1）并联级可以将第一电流传送到DAC的电流求和节点。（N-M）级可以包括电阻网络和第二对开关，并且可以将第二电流传递到级的电阻网络。每个电阻网络可以根据对应于电阻网络的级的二进制权重来缩放分别传递的电流，并且可以将缩放的电流传送到一对电流求和节点。（N-M）级中的至少一个可以与其余级分离。

4. 发明申请

US20150162933A1 METHOD FOR DIGITAL ERROR CORRECTION FOR BINARY SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) 有权
标题翻译：用于二进制连续逼近的模数转换器（ADC）的数字误差校正方法
公开(公告)号：US20150162933A1
公开(公告)日：2015-06-11
申请号：US14559178
申请日：2014-12-03
申请人： STMicroelectronics International N.V.
发明人： Francesca Girardi , Alberto Minuti , Germano Nicollini , Marco Zamprogno
IPC分类号： H03M1/46 , H03M1/08 , H03M1/68 , H03M1/00
CPC分类号： H03M1/46 , H03M1/001 , H03M1/0617 , H03M1/069 , H03M1/0845 , H03M1/1071 , H03M1/124 , H03M1/468 , H03M1/687 , H03M1/765 , H03M1/804
摘要： An analog input voltage is converted to a digital code by, generating a first set of confirmed bits based on a first series of comparisons of an output of a digital-to-analog converter with the analog input voltage and generating a second set of confirmed bits based on a second series of comparisons of the output of the digital-to-analog converter with the analog input voltage. The first set of confirmed bits is independent of the second series of comparisons. The bits of the digital output code corresponding to the analog input voltage are generated based on the first set of confirmed bits, the second set of confirmed bits and a constant value representative of a voltage shift introduced in the digital-to-analog converter between the first series of comparisons and the second series of comparisons.
摘要翻译：模拟输入电压通过基于数模转换器的输出与模拟输入电压的第一系列比较来产生第一组确认位，并产生第二组确认位，从而转换为数字代码基于数模转换器的输出与模拟输入电压的第二系列比较。第一组确认位与第二系列比较无关。对应于模拟输入电压的数字输出代码的位是基于第一组确认位，第二组确认位和表示在数模转换器中引入的电压偏移的常数值来生成的第一系列比较和第二系列比较。

5. 发明授权

US08984035B2 Channel select filter apparatus and method 有权
标题翻译：通道选择滤波装置及方法
公开(公告)号：US08984035B2
公开(公告)日：2015-03-17
申请号：US13145748
申请日：2010-01-27
申请人： Andrew Martin Mallinson
发明人： Andrew Martin Mallinson
IPC分类号： G06J1/00 , G06G7/02 , B60N2/00
CPC分类号： H03H17/0248 , B60N2/002 , H03H15/00 , H03M1/687 , H03M1/745 , H03M1/747
摘要： Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non-radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital-to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition.
摘要翻译：描述通道选择滤波器电路。一个电路实现了一个乘法元件和数 - 模转换器作为差分电流模式器件。实现乘法元件的另一个电路和具有加权相加的数模转换器，在数模转换器和乘法器组合的乘法之后延迟。在一个这样的电路中，基本相等的电流源幅度在电路的不同列中。另一个具有基本上相等的电流源幅度的这种电路使用非基数2。具有基本相等的电流源幅度的另一个这样的电路具有部分分割。另一电路实现了乘法元件和数模转换器，具有部分分段，元件的加扰位分配。如这里所述，一个这样的电路对等加权的片段进行比特分配。另一个电路实现了具有选择性地启用重复的电流源装置的乘法元件和数模转换器。另一电路实现了具有可变有效长度的数模转换器的乘法元件和数 - 模转换器。在一个这样的电路中，如本文所述，乘法器元件的一个或多个电流源被取消选择以去除乘法器元件的噪声贡献。复合滤波器电路包括一对实际有限脉冲响应滤波器电路，其在当前域中执行加法和减法，共享公共电阻网络以执行加权相加。一个这样的电路还包括第二对实际有限脉冲响应滤波器电路，其在当前域中执行加法和减法，共享第二公共电阻网络以执行加权相加。

6. 发明申请

US20150070074A1 CIRCUITRY AND METHODS FOR USE IN MIXED-SIGNAL CIRCUITRY 有权
标题翻译：用于混合信号电路的电路和方法
公开(公告)号：US20150070074A1
公开(公告)日：2015-03-12
申请号：US14473706
申请日：2014-08-29
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Ian Juso DEDIC , Saul Darzy , Gavin Lambertus Allen
IPC分类号： H03K17/16
CPC分类号： H03K17/145 , H03K17/162 , H03K17/302 , H03M1/0617 , H03M1/662 , H03M1/687 , H03M1/745 , H03M1/747
摘要： Switching circuitry for use in a digital-to-analogue converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.
摘要翻译：用于数模转换器的开关电路，所述电路包括：公共节点; 第一和第二输出节点; 以及多个开关，其连接在所述公共节点与所述第一和第二输出节点之间，并且可在基于输入数据的一系列时钟周期的每个时钟周期中工作，以将所述公共节点导电地连接到所述第一或第二输出节点多个路径中的给定一个路径，其中所述电路被布置为使得沿着从所述公共节点到所述第一或第二输出节点的每个所述路径串行地提供数据控制的开关和时钟控制的开关。

7. 发明授权

US08907831B1 High-resolution digital to analog converter 有权
标题翻译：高分辨率数模转换器
公开(公告)号：US08907831B1
公开(公告)日：2014-12-09
申请号：US14136728
申请日：2013-12-20
申请人： Maxim Integrated Products, Inc.
发明人： Syed Amir Aftab
IPC分类号： H03M1/66 , H03M1/68 , H03M1/00 , H03M1/78 , H03M1/74
CPC分类号： H03M1/68 , H03M1/00 , H03M1/687 , H03M1/747 , H03M1/765 , H03M1/785
摘要： A system includes an N-bit digital-to-analog converter and an M-bit sub-digital-to-analog converter. The N-bit digital-to-analog converter includes 2N resistances connected in series across first and second reference voltages and converts N most significant bits of B bits of data. The M-bit sub-digital-to-analog converter converts M least significant bits of the B bits of data. The M-bit sub-digital-to-analog converter includes a first converter that converts a voltage across one of the 2N resistances to a first current, a current-mode digital-to-analog converter that interpolates the first current and outputs a second current, and a second converter that converts the second current to an output voltage representing the N most significant bits and the M least significant bits of the B bits of data.
摘要翻译：一个系统包括一个N位数模转换器和一个M位子数模转换器。 N位数模转换器包括在第一和第二参考电压上串联连接的2N个电阻，并且转换B位数据的N个最高有效位。 M位子数字到模拟转换器转换B位数据的M个最低有效位。 M位子数模转换器包括将2N个电阻中的一个电压转换为第一电流的第一转换器，内插第一电流的电流模式数模转换器，并输出第二电流电流和第二转换器，其将第二电流转换成表示数据的B位的N个最高有效位和M个最低有效位的输出电压。

8. 发明授权

US08599057B2 Digital-to-analog converter 有权
标题翻译：数模转换器
公开(公告)号：US08599057B2
公开(公告)日：2013-12-03
申请号：US13159856
申请日：2011-06-14
申请人： Yu-Jen Lai , Mei-Chen Chuang , Wen-Shen Chou
发明人： Yu-Jen Lai , Mei-Chen Chuang , Wen-Shen Chou
IPC分类号： H03M1/66
CPC分类号： H03M1/1061 , H03M1/687 , H03M1/745 , H03M1/747
摘要： A system and method for converting a digital signal to an analog signal is provided. The present disclosure provides a digital-to-analog converter (DAC) that can convert a large bit value digital signal to a corresponding analog signal. In accordance with an embodiment, a method comprises receiving portions of a digital signal by a plurality of sub-DACs; converting the portions of the digital signal to a corresponding analog signal by the plurality of sub-DACs; biasing one or more of the plurality of sub-DACs; and calibrating the portions of a digital signal by one or more calibration elements.
摘要翻译：提供了一种将数字信号转换为模拟信号的系统和方法。本公开提供了一种数模转换器（DAC），其可以将大位值数字信号转换为对应的模拟信号。根据实施例，一种方法包括：通过多个子DAC接收数字信号的部分; 通过所述多个子DAC将所述数字信号的所述部分转换成相应的模拟信号; 偏置所述多个子DAC中的一个或多个; 以及通过一个或多个校准元件校准数字信号的部分。

9. 发明申请

US20130293405A1 SEGMENTED DIGITAL-TO-ANALOG CONVERTER HAVING WEIGHTED CURRENT SOURCES 有权
标题翻译：具有加权电流源的分段数字到模拟转换器
公开(公告)号：US20130293405A1
公开(公告)日：2013-11-07
申请号：US13747892
申请日：2013-01-23
申请人： Italo Carlos Medina Sánchez-Castro
发明人： Italo Carlos Medina Sánchez-Castro
IPC分类号： H03M1/78
CPC分类号： H03M1/785 , H03M1/687 , H03M1/745 , H03M1/765
摘要： A digital input to a digital-to-analog converter (DAC) is divided into a most significant portion and a lesser significant portion. At least one tap voltage generator generates a plurality of voltages, preferably using a resistor string. A decoder decodes at least one sub-word that forms the lesser significant portion to generate a corresponding at least one control signal. A switching unit accesses voltages generated by the at least one tap voltage generator in response to the at least one control signal. A scaled current generator generates a respective weighted current from each accessed voltage. An output stage combines all the weighted currents with a voltage that is an analog representation of the most significant portion of the digital input to generate an analog approximation of the entire digital input.
摘要翻译：数模转换器（DAC）的数字输入被分为最重要的部分和较小的显着部分。至少一个抽头电压发生器产生多个电压，优选使用电阻串。解码器解码形成较小有效部分的至少一个子字，以生成对应的至少一个控制信号。开关单元响应于至少一个控制信号访问由至少一个抽头电压发生器产生的电压。定标电流发生器从每个访问电压产生相应的加权电流。输出级将所有加权电流与作为数字输入的最高有效部分的模拟表示的电压组合以产生整个数字输入的模拟近似。

10. 发明申请

US20130120176A1 RESISTIVE DIGITAL-TO-ANALOG CONVERSION 有权
标题翻译：电阻数字到模拟转换
公开(公告)号：US20130120176A1
公开(公告)日：2013-05-16
申请号：US13296185
申请日：2011-11-14
申请人： Ark-Chew WONG , Jonathan Muller
发明人： Ark-Chew WONG , Jonathan Muller
IPC分类号： H03M1/66
CPC分类号： H03M1/808 , H03M1/1061 , H03M1/687 , H03M1/785
摘要： Examples of resistive digital-to-analog converter (RDAC) circuits are provided herein. RDAC circuits may provide an analog output signal derived from an n-bit digital input signal. In one example, an RDAC circuit may include a plurality of resistive circuit branches. Each resistive circuit branch may be arranged in a pull up/pull down network configuration. For example, an RDAC circuit may include a plurality of resistive circuit branches positioned in parallel. In an example, each of the plurality of resistive circuit branches may include a first inverter circuit, a second inverter circuit, and a resistive component. The RDAC circuit may include an output node for providing the analog output signal. Additionally, methods are provided for converting an analog output signal derived from an n-bit digital input signal.
摘要翻译：本文提供了电阻数模转换器（RDAC）电路的示例。 RDAC电路可以提供从n位数字输入信号导出的模拟输出信号。在一个示例中，RDAC电路可以包括多个电阻电路分支。每个电阻电路分支可以布置成上拉/下拉网络配置。例如，RDAC电路可以包括并联设置的多个电阻电路分支。在一个示例中，多个电阻电路分支中的每一个可以包括第一反相器电路，第二反相器电路和电阻部件。 RDAC电路可以包括用于提供模拟输出信号的输出节点。此外，提供了用于转换从n位数字输入信号导出的模拟输出信号的方法。

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