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21. 发明授权

US5938758A Microprocessor having function of prefetching instruction 失效
标题翻译：具有预取指令功能的微处理器
公开(公告)号：US5938758A
公开(公告)日：1999-08-17
申请号：US933579
申请日：1997-09-19
申请人： Takao Katayama , Shinichi Yamaura , Keiichi Yoshioka , Kazuhiko Hara
发明人： Takao Katayama , Shinichi Yamaura , Keiichi Yoshioka , Kazuhiko Hara
IPC分类号： G06F9/38 , G06F9/32 , G06F9/46 , G06F9/48 , G06F13/32 , G06F13/00
CPC分类号： G06F9/32 , G06F9/3802
摘要： A microprocessor having an instruction prefetch function includes a storage circuit in which an instruction externally supplied to the microprocessor via an external interface is stored, a first latch circuit which latches a write address value of the storage circuit in response to an interrupt signal externally supplied to the microprocessor, and an internal interrupt signal outputting circuit which compares a read address value of the storage circuit indicating the instruction stored in the storage circuit with the write address value supplied from the first latch circuit and which generates the internal interrupt signal only when the read address value and the write address value coincide with each other. The microprocessor processes an interrupt process in response to the internal interrupt signal.
摘要翻译：具有指令预取功能的微处理器包括存储电路，其中存储经由外部接口向外部提供给微处理器的指令，第一锁存电路，响应于外部提供给中断信号而锁存存储电路的写入地址值微处理器和内部中断信号输出电路，其将指示存储在存储电路中的指令的存储电路的读取地址值与从第一锁存电路提供的写入地址值进行比较，并且仅在读取时产生内部中断信号地址值和写入地址值彼此一致。微处理器响应于内部中断信号处理中断过程。

22. 发明授权

US5596761A Central processing unit with internal register initializing means 失效
标题翻译：具有内部寄存器初始化手段的中央处理单元
公开(公告)号：US5596761A
公开(公告)日：1997-01-21
申请号：US101399
申请日：1993-08-02
申请人： Keiichi Yoshioka , Takashi Yasui , Shinichi Yamaura
发明人： Keiichi Yoshioka , Takashi Yasui , Shinichi Yamaura
IPC分类号： G06F9/32 , G06F9/38 , G06F9/00
CPC分类号： G06F9/3861 , G06F9/32
摘要： A central processing unit (CPU) carries out selected reset interruption processing by using a vector address preset in accordance with an interruption source to generate an address to a data table whose contents are used to initialize selected registers. In this manner, the CPU can be reset without having first stored the processing state of the CPU in response to a reset interrupt request, without the need for extensive dedicated reset hardware, and with the ability to select desired reset values that can differ as between different interrupts and can be changed from time to time.
摘要翻译：中央处理单元（CPU）通过使用根据中断源预设的向量地址来执行所选择的复位中断处理，以将内容生成到其内容用于初始化所选择的寄存器的数据表。以这种方式，CPU可以被复位而不需要首先存储CPU的处理状态，而不需要广泛的专用复位硬件，并且具有选择期望的复位值的能力，所述复位值可以不同不同的中断，可以不时更改。

23. 发明授权

US5161229A Central processing unit 失效
标题翻译：中央处理器
公开(公告)号：US5161229A
公开(公告)日：1992-11-03
申请号：US533383
申请日：1990-06-05
申请人： Takashi Yasui , Keiichi Yoshioka , Shinichi Yamaura
发明人： Takashi Yasui , Keiichi Yoshioka , Shinichi Yamaura
IPC分类号： G06F9/48 , G06F9/38
CPC分类号： G06F9/3861
摘要： A central processing unit has a plurality of control sections; a device for selectively operating and unoperating the control sections by an external interrruption signal; and a device for processing an interruption sequence with respect to the interruption signal by the operations of the control sections in a state in which the control sections are operated. The control processing unit may be constructed such that the control sections are composed of two control sections and one of the two control sections processes a normal instruction sequence and is unoperated by the interruption signal, and the other of the two control sections is operated at the times of the normal instruction and interruption and processes the interruption sequence in addition to the normal instruction.
摘要翻译：中央处理单元具有多个控制部分; 用于通过外部中断信号选择性地操作和不操作所述控制部分的装置; 以及用于在控制部分被操作的状态下通过控制部分的操作来处理关于中断信号的中断序列的装置。控制处理单元可以被构造成使得控制部分由两个控制部分组成，并且两个控制部分中的一个控制部分处理正常指令序列并且由中断信号进行未操作，并且两个控制部分中的另一个在正常指令的次数和中断，并处理除了正常指令之外的中断序列。

24. 发明授权

US5019186A Process for producing chromium-containing steel sheet hot-dip plated with aluminum 失效
标题翻译：生产含铝热镀锌钢板的方法
公开(公告)号：US5019186A
公开(公告)日：1991-05-28
申请号：US539968
申请日：1990-06-15
申请人： Yasushi Kato , Keiichi Yoshioka , Osamu Hashimoto
发明人： Yasushi Kato , Keiichi Yoshioka , Osamu Hashimoto
IPC分类号： C23C2/02 , C23C2/12
CPC分类号： C23C2/02 , Y10T428/12757
摘要： A method of producing a chromium-containing steel sheet hot-dip plated with aluminum. A steel sheet containing not less than about 3 wt % of chromium is pre-plated at each side thereof with an iron-phosphor alloy so that a pre-plating layer of the iron-phosphor alloy about 0.05 to 3.0 .mu.m thick is formed on each side of the steel sheet. The steel sheet is heated and then subjected to an aluminum hot-dip plating by being dipped in a bath of molten aluminum or a molten aluminum alloy. An undercoat nickel plating layer may be formed on the steel sheet in advance of pre-plating with the iron-phosphor alloy.

25. 发明授权

US4452649A Motorcycle disc braking materials of a low carbon martensitic stainless steel 失效
标题翻译：摩托车盘式制动材料的低碳马氏体不锈钢
公开(公告)号：US4452649A
公开(公告)日：1984-06-05
申请号：US448901
申请日：1982-12-03
申请人： Keiichi Yoshioka , Noboru Kinoshita , Yutaka Ono
发明人： Keiichi Yoshioka , Noboru Kinoshita , Yutaka Ono
IPC分类号： C22C38/00 , B62K11/00 , B62L1/00 , C22C38/38 , F16D65/12 , F16D69/02 , C22C38/40
CPC分类号： F16D65/125 , C22C38/38 , F16D69/027
摘要： This invention belongs to the technical field of martensitic stainless steels and the moderate hardness, toughness and corrosion resistance required for motorcycle braking disc materials can be provided only by quenching at a broad range of quenching temperature by restraining the content of C+N in the steels to 0.04-0.10% and containing 1.0-2.5% of Mn and 10.0-14.5% of Cr.
摘要翻译： PCT No.PCT / JP82 / 00210 Sec。 371日期1982年12月3日 102（e）1982年12月3日日期PCT提交1982年5月28日PCT公布。出版物WO82 / 04268 日本1982年12月9日。本发明属于马氏体不锈钢的技术领域，摩托车制动盘材料所要求的适度的硬度，韧性和耐腐蚀性只能通过抑制内容物在宽范围的淬火温度下淬火来提供的钢中的C + N为0.04-0.10％，含有1.0-2.5％的Mn和10.0-14.5％的Cr。

26. 发明授权

US4256486A Martensitic stainless steel having excellent weldability and workability for structural use 失效
标题翻译：具有优异的焊接性和结构用加工性的马氏体不锈钢
公开(公告)号：US4256486A
公开(公告)日：1981-03-17
申请号：US62403
申请日：1979-07-31
申请人： Keiichi Yoshioka , Noboru Kinoshita , Yutaka Ono , Nobuo Ohashi
发明人： Keiichi Yoshioka , Noboru Kinoshita , Yutaka Ono , Nobuo Ohashi
IPC分类号： C22C38/00 , C22C38/18 , C22C38/38 , C22C38/16
CPC分类号： C22C38/38 , C22C38/18
摘要： Martensitic stainless steel having excellent weldability and workability for structural use is obtained by limiting each content of carbon and nitrogen to the low value less than 0.02% and the content of nickel to less than 0.1% and by satisfying the following requirement.Cr equivalent=[%Cr]+0.4.times.[%Si]-0.4.times.[%Mn]-0.7.times.[%Ni]-0.6.times.[%Cu]-35.times.[%C]-10.times.[%N].ltoreq.10.5,wherein % means weight % of the element in steel.
摘要翻译：具有优异的焊接性和结构用加工性的马氏体系不锈钢是通过将碳和氮的每个含量限制在小于0.02％的低值和镍含量小于0.1％并满足以下要求来获得的。 Cr当量= [％Cr] + 0.4x [％Si] -0.4x [％Mn] -0.7x [％Ni] -0.6x [％Cu] -35x [％C] -10x [％N] 10.5，其中％表示钢中元素的重量％。

27. 发明申请

US20060072354A1 Information processing device and method, recording medium, and program 有权
标题翻译：信息处理装置和方法，记录介质和程序
公开(公告)号：US20060072354A1
公开(公告)日：2006-04-06
申请号：US10522444
申请日：2003-07-23
申请人： Kensuke Ohnuma , Hitoshi Kimura , Shinichi Wakai , Keiichi Yoshioka , Shingo Utsuki , Hidetoshi Ichioka
发明人： Kensuke Ohnuma , Hitoshi Kimura , Shinichi Wakai , Keiichi Yoshioka , Shingo Utsuki , Hidetoshi Ichioka
IPC分类号： G11C11/22
CPC分类号： H04N21/47214 , H04N5/44543 , H04N5/76 , H04N5/765 , H04N5/782 , H04N21/4532 , H04N21/4828
摘要： To make it possible to reserve recording of a program without imposing a large load on a user. A server 2-1 transmits program attribute information to a video recording and reproducing apparatus 11 via a network 1. The program attribute information is constituted by program attribute names and program attribute retrieval conditions. The video recording and reproducing apparatus 11 causes a display apparatus 12 to display a list of the program attribute names. The user selects a program attribute name, to which a program that the user wishes to reserve for recording seems to be most closely related, out of this list. The video recording and reproducing apparatus 11 compares retrieval conditions corresponding to the selected program attribute name and EPG information and, when the retrieval conditions are satisfied, records a program represented by the EPG in a recording reservation list. It is possible to apply the invention to a hard disk video recorder.
摘要翻译：为了能够在不对用户施加大的负载的情况下保留节目的记录。服务器2-1经由网络1将节目属性信息发送到视频记录和再现装置11。程序属性信息由程序属性名称和程序属性检索条件构成。视频记录和再现装置11使显示装置12显示节目属性名称的列表。用户选择一个程序属性名称，用户希望保留的程序记录似乎与此列表最相关。视频记录和再现装置11比较与所选择的节目属性名称和EPG信息相对应的检索条件，并且当满足检索条件时，将由EPG表示的节目记录在记录预约列表中。可以将本发明应用于硬盘录像机。

28. 发明申请

US20060023116A1 Program-display control apparatus and program-display control method 失效
标题翻译：程序显示控制装置和程序显示控制方法
公开(公告)号：US20060023116A1
公开(公告)日：2006-02-02
申请号：US10515664
申请日：2003-05-22
申请人： Shunsuke Kunieda , Shingo Utsuki , Keiichi Yoshioka , Kae Nagano
发明人： Shunsuke Kunieda , Shingo Utsuki , Keiichi Yoshioka , Kae Nagano
IPC分类号： H04N7/01
CPC分类号： H04N5/44543 , H04N21/4314 , H04N21/435 , H04N21/4622 , H04N21/4821 , H04N21/84
摘要： A program-display control apparatus can display information on each of a plurality of programs in a state that can be recognized by the user with ease without regard to the display configuration of the display data of the program. A display-configuration modification unit changes the display configurations of the program table of a BS digital broadcast, the program table of a ground wave broadcast, and a WEB program table into a new display configuration which increases the amount of information on the programs without regard to the display configuration of each of the programs. Furthermore, a program-table creation unit creates display data according to the new display configuration and outputs the display data.
摘要翻译：节目显示控制装置可以在不考虑节目的显示数据的显示配置的情况下容易地以用户可以识别的状态来显示关于多个节目中的每一个的信息。显示配置修改单元将BS数字广播的节目表的显示配置，地面波广播的节目表和WEB节目表改变为新的显示配置，这增加了节目上的信息量，而不考虑到每个程序的显示配置。此外，程序表创建单元根据新的显示配置创建显示数据并输出显示数据。

29. 发明授权

US06748514B2 Parallel processor and image processing system for simultaneous processing of plural image data items without additional circuit delays and power increases 有权
标题翻译：并行处理器和图像处理系统，用于同时处理多个图像数据项，而没有额外的电路延迟和功率增加
公开(公告)号：US06748514B2
公开(公告)日：2004-06-08
申请号：US09782989
申请日：2001-02-14
申请人： Keiichi Yoshioka
发明人： Keiichi Yoshioka
IPC分类号： G06F1516
CPC分类号： G06F15/8007
摘要： A parallel processor and an image processing system incorporating such processor are disclosed. Control signals in the parallel processor are generated by an instruction sequence control unit, and divided into two: global control signals supplied to a local signal generator of arbitrary selected processor element group; and local control signals buffered by the local control signal generator and then supplied exclusively to the processor elements included in arbitrary selected processor element group. This construction of the processor alleviates deterioration in device characteristics and undesirable increase in driving power requirements.
摘要翻译：公开了并入处理器和并入处理器的图像处理系统。并行处理器中的控制信号由指令序列控制单元产生，并被分成两个：提供给任意选择的处理器单元组的本地信号发生器的全局控制信号; 以及由本地控制信号发生器缓冲的本地控制信号，然后专门提供给包括在任意选择的处理器元件组中的处理器元件。处理器的这种结构减轻了设备特性的恶化和驱动功率要求的不期望的增加。

30. 发明授权

US06651236B2 Semiconductor integrated circuit device, and method of placement and routing for such device 有权
公开(公告)号：US06651236B2
公开(公告)日：2003-11-18
申请号：US09951071
申请日：2001-09-13
申请人： Junji Ichimiya , Keiichi Yoshioka
发明人： Junji Ichimiya , Keiichi Yoshioka
IPC分类号： G06F1750
CPC分类号： H01L27/118 , G06F17/5068
摘要： A semiconductor integrated circuit device fabricated with reduced size and wiring to alleviate wiring delay, and an improved placement and routing method of the building-block type for appropriate use in deep-submicron processes for fabricating such semiconductor device. This semiconductor integrated circuit device includes at least a plurality of integrated circuit blocks to be interconnected by wiring, and a terminal cell including a terminal target metal that is different from, and formed in a layer higher at least by one layer than, ordinary target metals originally included in a block netlist. The interconnection among the integrated circuit blocks is carried out by way of the block terminals provided in circumferential edge portions on the block layout and the terminal target of the terminal cell.

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