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21. 发明申请

US20070030731A1 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070030731A1
公开(公告)日：2007-02-08
申请号：US11496458
申请日：2006-08-01
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C11/5642
摘要： A sense amplifier has first and second input nodes. A reference memory cell is connected to the first input node. To the second input node, a constant current source circuit and a main memory cell are connected via a first transistor and a second transistor, respectively. A current mirror type load circuit is provided as a load circuit of the reference memory cell and the main memory cell. When a threshold voltage of the reference memory cell is adjusted, the first transistor is turned on and the second transistor is turned off. When the threshold voltage of the memory cell is adjusted at verification of writing to/erasing from the memory cell, the first transistor is turned off and the second transistor is turned on.
摘要翻译：读出放大器具有第一和第二输入节点。参考存储单元连接到第一输入节点。对于第二输入节点，恒流源电路和主存储单元分别经由第一晶体管和第二晶体管连接。提供电流镜式负载电路作为参考存储单元和主存储单元的负载电路。当调整参考存储单元的阈值电压时，第一晶体管导通，第二晶体管截止。当在从存储单元写入/擦除的验证中调整存储单元的阈值电压时，第一晶体管截止，第二晶体管导通。

22. 发明授权

US07126855B2 Semiconductor device that enables simultaneous read and write/read operation 失效
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US07126855B2
公开(公告)日：2006-10-24
申请号：US11125073
申请日：2005-05-10
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义作为数据擦除单位的存储单元的范围。半导体器件具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作以在第一和第二组中的另一个中进行数据写入或擦除操作的第一和第二存储体。

23. 发明申请

US20060227645A1 Nonvolatile semiconductor memory device which stores multivalue data 失效
标题翻译：存储多值数据的非易失性半导体存储器件
公开(公告)号：US20060227645A1
公开(公告)日：2006-10-12
申请号：US11401421
申请日：2006-04-11
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C5/14
CPC分类号： G11C11/5628 , G11C16/0416 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： A voltage generating circuit supplies first gate voltage to the control gate of a memory cell for a first control time period and supplies write voltage to the drain for a first write time period which is shorter than the first control time period when an operation of writing data into the memory cell is started. As the verify result, if it is detected that a data amount written into the memory cell is insufficient, the voltage generating circuit supplies second control voltage obtained by raising the first control gate voltage by constant voltage to the control gate for a time period which is shorter than the first control time period and supplies write voltage to the drain for a second write time period which is shorter than the first write time period.
摘要翻译：电压产生电路将第一栅极电压提供给存储单元的控制栅极用于第一控制时间段，并且在写入数据的操作时将写入电压提供给漏极，用于比第一控制时间段短的第一写入时间段进入内存单元开始。作为验证结果，如果检测到写入存储单元的数据量不足，则电压产生电路将通过将第一控制栅极电压提高到恒定电压而获得的第二控制电压提供给控制栅极，时间段为比第一控制时间段短，并将写入电压提供给漏极，持续比第一写入时间段短的第二写入时间段。

24. 发明申请

US20050207247A1 Semiconductor device that enables simultaneous read and write/read operation 失效
公开(公告)号：US20050207247A1
公开(公告)日：2005-09-22
申请号：US11125073
申请日：2005-05-10
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/00 , G11C5/00 , G11C8/12 , G11C16/10 , G11C16/26
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

25. 发明申请

US20050169081A1 Semiconductor storage apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US20050169081A1
公开(公告)日：2005-08-04
申请号：US11019271
申请日：2004-12-23
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C16/06 , G11C7/02 , G11C7/06 , G11C7/12 , G11C16/04 , G11C16/24 , G11C11/34
CPC分类号： G11C7/062 , G11C7/02 , G11C7/12 , G11C16/24
摘要： A semiconductor storage apparatus comprises a cell array including memory cells and reference cells, normal column selection transistors connected to columns of the memory cells, a normal data line array including normal data lines connected to columns of the memory cells, first dummy data lines formed of a same wiring layer of which the normal data lines are formed, a normal data line charging circuit, reference column selection transistors connected to reference columns of the reference cells, a reference data line array including reference data lines formed of a same wiring layer of which the normal data lines are formed, second dummy data lines formed of a same wiring layer of which the reference data lines are formed, a reference data line charging circuit, a first dummy data line charging circuit, a second dummy data line charging circuit, and a sense amplifier which senses data stored in the memory cells.
摘要翻译：半导体存储装置包括具有存储单元和参考单元的单元阵列，连接到存储单元的列的正常列选择晶体管，包括连接到存储单元的列的普通数据线的正常数据线阵列，第一虚拟数据线由形成正常数据线的相同布线层，正常数据线充电电路，连接到参考单元的参考列的参考列选择晶体管，包括由相同布线层形成的参考数据线的参考数据线阵列形成正常的数据线，由形成基准数据线的相同布线层形成的第二虚拟数据线，参考数据线充电电路，第一虚拟数据线充电电路，第二虚拟数据线充电电路和感测放大器，其感测存储在存储单元中的数据。

26. 发明授权

US5431141A Electronic throttle system 失效
标题翻译：电子节气门系统
公开(公告)号：US5431141A
公开(公告)日：1995-07-11
申请号：US086210
申请日：1993-07-06
申请人： Hiroshi Kanazawa , Fumio Tajima , Yasuhiko Honda , Yasushi Sasaki , Teruhiko Minegishi , Yoshikatu Hashimoto , Tatsuya Yoshida , Yuzo Kadomukai
发明人： Hiroshi Kanazawa , Fumio Tajima , Yasuhiko Honda , Yasushi Sasaki , Teruhiko Minegishi , Yoshikatu Hashimoto , Tatsuya Yoshida , Yuzo Kadomukai
IPC分类号： F02D9/02 , B60K26/04 , F02D11/10
CPC分类号： F02D11/10 , B60K26/04 , F02D11/107 , F02D2011/103 , Y02T10/42
摘要： On one side of a valve shaft, there are provided an accelerator drum connected to an accelerator pedal by an accelerator wire, a return spring for urging the accelerator drum in a valve closing direction, and an accelerator sensor for detecting rotation of the accelerator drum and transmitting a detected signal to a host system. On the other side of the valve shaft, there are provided a large-diameter gear and an opening sensor. An armature of a solenoid clutch is attached to the gear and held on a motor shaft via a slide bearing. Thus, the motor, the solenoid clutch and the throttle valve are arranged into a U-shaped form for interconnection through four gears.
摘要翻译：在阀轴的一侧，设有通过加速器线连接到加速器踏板的加速器鼓，用于沿关闭方向推压加速鼓的复位弹簧和用于检测加速鼓的旋转的加速器传感器，将检测到的信号发送到主机系统。在阀轴的另一侧，设置有大直径齿轮和开口传感器。电磁离合器的电枢连接到齿轮上，并通过滑动轴承保持在电动机轴上。因此，马达，电磁离合器和节流阀被布置成U形形状，用于通过四个齿轮互连。

27. 发明授权

US07751252B2 Semiconductor memory with a reference current generating circuit having a reference current generating section and an amplifier section 有权
标题翻译：具有参考电流产生电路的半导体存储器，具有参考电流产生部分和放大器部分
公开(公告)号：US07751252B2
公开(公告)日：2010-07-06
申请号：US12273979
申请日：2008-11-19
申请人： Jin Kashiwagi , Yasuhiko Honda , Yoshihiko Kamata
发明人： Jin Kashiwagi , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G11C16/28
CPC分类号： G11C7/14 , G11C16/28
摘要： A semiconductor memory capable of storing and reading data in a memory cell for holding the data corresponding to a threshold voltage has a reference current generating circuit having a reference current generating section and an amplifier section.
摘要翻译：能够存储和读取存储单元中用于保持对应于阈值电压的数据的数据的半导体存储器具有参考电流产生电路，其具有参考电流产生部分和放大器部分。

28. 发明申请

US20090161464A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090161464A1
公开(公告)日：2009-06-25
申请号：US12338041
申请日：2008-12-18
申请人： Tatsuro MIDORIKAWA , Yasuhiko Honda , Gyosho Chin
发明人： Tatsuro MIDORIKAWA , Yasuhiko Honda , Gyosho Chin
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C5/147 , G11C8/08 , G11C11/5642 , G11C16/28 , G11C16/30 , G11C2211/5621
摘要： A semiconductor memory device includes a memory cell array which includes a plurality of memory cells which are arrayed in a matrix at intersections between a plurality of word lines and a plurality of bit lines and a power supply circuit which includes a first band gap reference circuit which outputs a first output voltage, and a second band gap reference circuit which outputs a second output voltage having lower temperature characteristics than the first output voltage on a low temperature side, and generates a power supply voltage on the basis of the second output voltage at a time of a data write operation of the memory cells.
摘要翻译：半导体存储器件包括存储单元阵列，其包括在多个字线和多个位线之间的交叉处以矩阵排列的多个存储器单元，以及包括第一带隙基准电路的电源电路，输出第一输出电压和第二带隙基准电路，其在低温侧输出具有比第一输出电压低的温度特性的第二输出电压，并且基于第二输出电压在第二输出电压存储单元的数据写入操作的时间。

29. 发明授权

US07477549B2 Reference current generating circuit of nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件的参考电流产生电路
公开(公告)号：US07477549B2
公开(公告)日：2009-01-13
申请号：US11763987
申请日：2007-06-15
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C11/34
CPC分类号： G11C7/14 , G11C11/5642 , G11C16/26 , G11C16/28 , G11C16/30
摘要： A reference current generating circuit has a plurality of current mirror circuits each having a mirror ratio different from another one, and generates a plurality of reference currents based on a current that flows to the reference memory cells. A plurality of sense amplifiers detects a current that flows to a selected memory cell based on the reference currents generated by the reference current generating circuit.
摘要翻译：参考电流产生电路具有多个电流镜电路，每个电流镜电路具有与另一个不同的镜面比，并且基于流向参考存储器单元的电流产生多个参考电流。多个读出放大器基于由参考电流产生电路产生的参考电流来检测流向所选存储单元的电流。

30. 发明授权

US07345919B2 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US07345919B2
公开(公告)日：2008-03-18
申请号：US11453830
申请日：2006-06-16
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/04
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device includes a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks. The semiconductor device further includes a first power supply line which is provided commonly for said plurality of cores and which provides a data reading power supply potential; a second power supply line which is provided commonly for said plurality of cores and which provides a data writing or erasing power supply potential; and a power supply line switching circuit which is provided for each of said plurality of cores and which selectively connects a corresponding one of said plurality of cores to said first power supply line or said second power supply line in accordance with whether said corresponding one of said plurality of cores is in a data read mode or a data write or erase mode.
摘要翻译：半导体器件包括包括多个核的存储单元阵列，每个所述核包括一个块或多个块。所述半导体器件还包括第一电源线，所述第一电源线通常为所述多个芯提供，并提供数据读取电源电位; 第二电源线，其为所述多个核心共同提供，并且提供数据写入或擦除电源电位; 以及电源线切换电路，其被设置用于所述多个芯中的每一个，并且根据所述多个核中的所述相应一个选择性地将所述多个核中的相应一个核连接到所述第一电源线或所述第二电源线多个核心处于数据读取模式或数据写入或擦除模式。

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