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1. 发明申请

US20120069683A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20120069683A1
公开(公告)日：2012-03-22
申请号：US13235391
申请日：2011-09-18
申请人： Yoshihiko KAMATA , Fumitaka Taniwaki , Hirotaka Kariya , Yuki Shimizu , Shirou Fujita
发明人： Yoshihiko KAMATA , Fumitaka Taniwaki , Hirotaka Kariya , Yuki Shimizu , Shirou Fujita
IPC分类号： G11C16/10 , G11C16/06
CPC分类号： G11C11/5642 , G11C16/10 , G11C16/26
摘要： According to one embodiment, a semiconductor storage device includes a cell array, an even line, an odd line, and sense amplifiers. The cell array includes memory cells holding data. The even line connects to the memory cells. The odd line connects to the memory cells. The memory cells connect to an odd column or the even column. Each the sense amplifiers selectively connect to the odd line or the even line. Each the sense amplifiers includes a latch circuit, a first transistor, a second transistor, and a third transistor. The latch circuit includes a first node and a second node, and holds the data supplied to the first node. The first transistor supplies read data to the latch circuit. The second transistor transfers the data held by the latch circuit to the wiring. The third transistor transfers the data held by the latch circuit to the wiring.
摘要翻译：根据一个实施例，半导体存储装置包括单元阵列，偶数行，奇数行和读出放大器。单元阵列包括保存数据的存储单元。偶数行连接到存储单元。奇数行连接到存储单元。存储单元连接到奇数列或偶数列。每个读出放大器选择性地连接到奇数行或偶数行。每个读出放大器包括锁存电路，第一晶体管，第二晶体管和第三晶体管。锁存电路包括第一节点和第二节点，并且保存提供给第一节点的数据。第一晶体管将读取数据提供给锁存电路。第二晶体管将由锁存电路保持的数据传送到布线。第三晶体管将由锁存电路保持的数据传送到布线。

2. 发明申请

US20090129148A1 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：US20090129148A1
公开(公告)日：2009-05-21
申请号：US12273979
申请日：2008-11-19
申请人： Jin KASHIWAGI , Yasuhiko HONDA , Yoshihiko KAMATA
发明人： Jin KASHIWAGI , Yasuhiko HONDA , Yoshihiko KAMATA
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C7/14 , G11C16/28
摘要： A semiconductor memory capable of storing and reading data in a memory cell for holding the data corresponding to a threshold voltage has a reference current generating circuit having a reference current generating section and an amplifier section.
摘要翻译：能够存储和读取存储单元中用于保持对应于阈值电压的数据的数据的半导体存储器具有参考电流产生电路，其具有参考电流产生部分和放大器部分。

3. 发明申请

US20090115500A1 VOLTAGE GENERATING CIRCUIT 失效
标题翻译：电压发生电路
公开(公告)号：US20090115500A1
公开(公告)日：2009-05-07
申请号：US12260366
申请日：2008-10-29
申请人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
发明人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/143 , G11C5/145 , H02M3/073 , H02M2001/0025 , H02M2001/0032 , Y02B70/16
摘要： A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.
摘要翻译：用于从输出端子输出电压的电压产生电路具有连接在输出端子与地之间的第一分压电路; 连接在输出端和第一分压电路之间的开关电路; 第一电压检测电路，输出与比较结果对应的第一泵浦信号; 连接在输出端子和地之间的第二分压电路; 第二电压检测电路，其输出与比较结果相对应的第二泵浦信号; 输出从电源电压提升的电压的泵电路; 以及升压电路，其具有一端与第一分压电路的分压电阻连接的电容元件。

4. 发明授权

US07813182B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07813182B2
公开(公告)日：2010-10-12
申请号：US12272118
申请日：2008-11-17
申请人： Yoshihiko Kamata , Takayuki Harima , Yasuhiko Honda
发明人： Yoshihiko Kamata , Takayuki Harima , Yasuhiko Honda
IPC分类号： G11C16/28
CPC分类号： G11C16/0483 , G11C7/06 , G11C7/062 , G11C11/5642 , G11C16/28 , G11C2207/063 , G11C2211/5634 , G11C2211/5645
摘要： A semiconductor memory has a first-stage amplifier circuit, wherein data stored in a memory cells is read based on a potential between an amplifier input MOS transistor and an amplifier reference MOS transistor, the potential being outputted from the first-stage amplifier circuit.
摘要翻译：半导体存储器具有第一级放大器电路，其中基于放大器输入MOS晶体管和放大器参考MOS晶体管之间的电位来读取存储在存储单元中的数据，该电位从第一级放大器电路输出。

5. 发明申请

US20090135657A1 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：US20090135657A1
公开(公告)日：2009-05-28
申请号：US12272118
申请日：2008-11-17
申请人： Yoshihiko KAMATA , Takayuki HARIMA , Yasuhiko HONDA
发明人： Yoshihiko KAMATA , Takayuki HARIMA , Yasuhiko HONDA
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C7/06 , G11C7/062 , G11C11/5642 , G11C16/28 , G11C2207/063 , G11C2211/5634 , G11C2211/5645
摘要： A semiconductor memory has a first-stage amplifier circuit, wherein data stored in a memory cells is read based on a potential between an amplifier input MOS transistor and an amplifier reference MOS transistor, the potential being outputted from the first-stage amplifier circuit.
摘要翻译：半导体存储器具有第一级放大器电路，其中基于放大器输入MOS晶体管和放大器参考MOS晶体管之间的电位来读取存储在存储单元中的数据，该电位从第一级放大器电路输出。

6. 发明申请

US20080253195A1 SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MOS TRANSISTOR HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND DATA READOUT METHOD THEREOF 审中-公开
标题翻译：半导体存储器件，其中包括具有充电累积层的MOS晶体管和控制门及其数据读出方法
公开(公告)号：US20080253195A1
公开(公告)日：2008-10-16
申请号：US12099514
申请日：2008-04-08
申请人： Yoshihiko Kamata
发明人： Yoshihiko Kamata
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/28 , G11C7/06 , G11C11/5642 , G11C16/24 , G11C2211/5634 , G11C2211/5645
摘要： A semiconductor memory device includes first and second memory cells and a sense amplifier. The first memory cell includes a MOS transistor and is capable of retaining n-bit (n is a natural number more than one) first data. The MOS transistor includes a charge accumulation layer and a control gate. The second memory cell retains second data. The second data is a criterion for the first data. The sense amplifier determines the first data read out from the first memory cell and amplifies the first data using a first reference level and a second reference level. The first reference level is obtained based on the second data read out from the second memory cell. The second reference level is generated inside based on the first reference level.
摘要翻译：半导体存储器件包括第一和第二存储器单元和读出放大器。第一存储单元包括MOS晶体管，并且能够保留n位（n是多于一个的自然数）第一数据。 MOS晶体管包括电荷累积层和控制栅极。第二存储单元保留第二数据。第二数据是第一数据的标准。读出放大器确定从第一存储器单元读出的第一数据，并使用第一参考电平和第二参考电平放大第一数据。基于从第二存储单元读出的第二数据获得第一参考电平。第二参考电平是根据第一参考电平在内部生成的。

7. 发明授权

US06617907B2 Voltage translator 失效
公开(公告)号：US06617907B2
公开(公告)日：2003-09-09
申请号：US10078356
申请日：2002-02-21
申请人： Yoshihiko Kamata
发明人： Yoshihiko Kamata
IPC分类号： H03L500
CPC分类号： G11C8/08 , G11C5/145 , H03K19/01721 , H03K19/018507
摘要： A voltage translator enabling a high speed non-selection switching with regard to the word line voltage. The voltage translator (10) includes one inverter (made up of transistors N1 and P1) arranged on the output side of the voltage transistor circuit, a feedback PMOS type transistor (P2), an NMOS type transistor (N4) having a earth terminal and controlled by the output signal from the other inverter newly added on the input side of the voltage translator circuit, an NMOS type transistor (N3) controlled by the word line, and a PMOS type transistor (P3) controlled by a signal given through an NOMS transistor (N2) connected with the output of the above newly added inverter located on the input side of the voltage translator circuit.

8. 发明申请

US20120113724A1 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：US20120113724A1
公开(公告)日：2012-05-10
申请号：US13235416
申请日：2011-09-18
申请人： Mario SAKO , Yoshihiko Kamata
发明人： Mario SAKO , Yoshihiko Kamata
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/06 , G11C16/26 , G11C29/789 , G11C29/82
摘要： According to one embodiment, a semiconductor memory includes a memory cell array including a plurality of memory cells, a sense amplifier circuit holding a verification result for the memory cells and including sense units, the sense units of each column block being connected in common to a first signal line, and a detecting circuit including a detecting unit. The detecting unit includes a first latch circuit which holds failure information in the memory cell arrays, and a second latch circuit which includes a first input terminal connected to the first signal line, a second input terminal connected to the first latch circuit, and a first output terminal connected to a second signal line.
摘要翻译：根据一个实施例，半导体存储器包括包括多个存储单元的存储单元阵列，保持存储单元的验证结果并包括感测单元的读出放大器电路，每个列块的感测单元共同连接到第一信号线和包括检测单元的检测电路。检测单元包括保存存储单元阵列中的故障信息的第一锁存电路和包括连接到第一信号线的第一输入端，连接到第一锁存电路的第二输入端和第一锁存电路的第二锁存电路，输出端子连接到第二信号线。

9. 发明申请

US20100238736A1 Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：US20100238736A1
公开(公告)日：2010-09-23
申请号：US12659092
申请日：2010-02-25
申请人： Yoshihiko Kamata , Jin Kashiwagi , Hikaru Mochizuki
发明人： Yoshihiko Kamata , Jin Kashiwagi , Hikaru Mochizuki
IPC分类号： G11C16/06 , G11C5/14 , G11C7/06
CPC分类号： G11C11/5628 , G11C16/3436
摘要： 1. A semiconductor storage device has a first MOS transistor connected at a first end thereof to a power supply and diode-connected; a second MOS transistor connected in parallel with the first MOS transistor; a memory cell connected between the second end of the first MOS transistor and ground, the memory cell capable of adjusting a current flowing through the memory cell; a third MOS transistor connected at a first end thereof to the power supply, and diode-connected; a fourth MOS transistor connected in parallel with the third MOS transistor; a fifth MOS transistor connected between the second end of the fourth MOS transistor and the ground and supplied at a gate thereof with the first reference voltage; and an amplifier circuit which compares the sense voltage with the comparison voltage, and which outputs a comparison result signal depending upon a result of the comparison.
摘要翻译：半导体存储装置的第一MOS晶体管的第一端与电源连接，二极管连接; 与第一MOS晶体管并联连接的第二MOS晶体管; 连接在第一MOS晶体管的第二端和地之间的存储单元，所述存储单元能够调节流过所述存储单元的电流; 第三MOS晶体管，其第一端连接到电源，二极管连接; 与第三MOS晶体管并联连接的第四MOS晶体管; 连接在第四MOS晶体管的第二端和地之间并在其栅极处提供第一参考电压的第五MOS晶体管; 以及放大器电路，其将感测电压与比较电压进行比较，并且根据比较结果输出比较结果信号。

10. 发明申请

US20100214837A1 NONVOLATILE SEMICONDUCTOR MEMORY WITH CHARGE STORAGE LAYERS AND CONTROL GATES 有权
标题翻译：具有充电储存层和控制栅的非易失性半导体存储器
公开(公告)号：US20100214837A1
公开(公告)日：2010-08-26
申请号：US12552563
申请日：2009-09-02
申请人： Mario SAKO , Jun Fujimoto , Noriyasu Kumazaki , Yasuhiko Honda , Yoshihiko Kamata
发明人： Mario SAKO , Jun Fujimoto , Noriyasu Kumazaki , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G11C16/04 , G11C11/00
CPC分类号： G11C5/147 , G11C16/0483 , G11C16/30
摘要： A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.
摘要翻译：非易失性半导体存储器包括存储单元阵列，位线，第一电压发生器和第二电压发生器。存储单元阵列包括存储单元。每个位线与相应的一个存储单元的电流路径的一端电连接。第一电压发生器，其能够经由第一输出端子向位线提供外部提供的第一电压或通过降低提供的并高于第一电压的第二电压而获得的第三电压，并且其与第一电压一样高第一电压。第二电压发生器，当第一电压发生器降低第二电压以产生第三电压时，能够将通过第二输出端降低第二电压而获得的第四电压提供给位线。

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