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21. 发明授权

US09153641B2 Wafer level package having cylindrical capacitor and method of fabricating the same 有权
标题翻译：具有圆柱形电容器的晶片级封装及其制造方法
公开(公告)号：US09153641B2
公开(公告)日：2015-10-06
申请号：US13752238
申请日：2013-01-28
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人： Seung Seoup Lee , Soon Gyu Yim
IPC分类号： H01L29/92 , H01L21/02 , H01L49/02 , H01L23/522 , H01L23/31
CPC分类号： H01L28/60 , H01L23/3114 , H01L23/5223 , H01L28/90 , H01L2224/131 , H01L2924/01002 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/19041 , H01L2924/014
摘要： Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer and having a first recess for exposing an upper surface of the inner electrode. A method of fabricating the wafer level package having a cylindrical capacitor is also provided.
摘要翻译：公开了一种具有圆柱形电容器的晶片级封装，其由于使用圆柱形电容器结构而能够增加静电容量，并且其包括其上形成有焊盘的晶片芯片和形成在其上的绝缘层，并露出焊盘连接到接合焊盘并延伸到绝缘层的一侧的再分配层，连接到再分配层并且具有中心开口的圆筒形外部电极，形成在外部电极的中心开口中的圆柱形内部电极，以便与外部电极分离，形成在外部电极和内部电极之间的电介质层和形成在绝缘层上以覆盖再分配层，内部电极，外部电极和电介质层的树脂密封部分，并且具有用于暴露内部电极的上表面的第一凹部。还提供了一种制造具有圆柱形电容器的晶片级封装的方法。

22. 发明授权

US09136269B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09136269B2
公开(公告)日：2015-09-15
申请号：US14526201
申请日：2014-10-28
申请人： SK hynix Inc.
发明人： Jung Ryul Ahn , Yun Kyoung Lee
IPC分类号： H01L27/108 , H01L21/02 , H01L29/92 , H01L23/522 , H01L27/105 , H01L49/02 , H01L21/28
CPC分类号： H01L27/10844 , H01L21/28008 , H01L23/5223 , H01L27/105 , H01L28/60 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer.
摘要翻译：半导体器件包括被划分为单元区域和沿第一方向限定的外围电路区域的半导体衬底，其中外围电路区域被划分为在基本上正交于第一方向的第二方向上限定的第一区域和第二区域; 栅极线形成在电池区域中的半导体衬底上并且布置在第二方向上; 以及包括在半导体衬底上的下电极，电介质层和上电极的电容器，其中第一和第二区域中的下电极在第一方向上彼此分离并在第一区域中彼此分离，电介质在第二区域中沿着下电极的表面形成层，并且在电介质层上形成上电极。

23. 发明授权

US08962472B2 Semiconductor device with self-aligned air gap and method for fabricating the same 有权
标题翻译：具有自对准气隙的半导体器件及其制造方法
公开(公告)号：US08962472B2
公开(公告)日：2015-02-24
申请号：US13844915
申请日：2013-03-16
申请人： SK Hynix Inc.
发明人： Il-Cheol Rho , Jong-Min Lee
IPC分类号： H01L21/764 , H01L29/92 , H01L27/108
CPC分类号： H01L21/7682 , H01L21/28008 , H01L21/764 , H01L21/76877 , H01L21/76886 , H01L27/10823 , H01L27/10855 , H01L29/92
摘要： A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成多个半导体结构，在半导体结构上形成层间电介质层，蚀刻层间电介质层，并且在半导体结构之间限定开放部分以露出衬底的表面，在开放部分的侧壁上形成牺牲隔离物，在开放部分中形成导电层图案，并使导电层图案和牺牲间隔物彼此到达，并且在开口部分的侧壁上限定气隙。

24. 发明授权

US08952748B2 Circuit and method for a multi-mode filter 有权
标题翻译：多模式滤波器的电路和方法
公开(公告)号：US08952748B2
公开(公告)日：2015-02-10
申请号：US13872727
申请日：2013-04-29
申请人： FutureWei Technologies, Inc.
发明人： Homero Guimaraes , Matthew Richard Miller
IPC分类号： H03K17/16 , H03K17/687 , H01L29/92 , G08C19/00 , H01L49/02
CPC分类号： G08C19/00 , H01L27/0805 , H01L28/40 , H01L29/94
摘要： An embodiment integrated circuit includes a first capacitive element including a first metal-oxide-semiconductor (MOS) capacitor and a second capacitive element coupled in parallel with the first capacitive element, where the second capacitive element includes a second MOS capacitor. Also, the integrated circuit includes a third capacitive element coupled in parallel with the first capacitive element and the second capacitive element, where the third capacitive element includes a first metal-insulator-metal (MIM) capacitor and a fourth capacitive element coupled in parallel with the first capacitive element, the second capacitive element, and the third capacitive element, where the fourth capacitive element includes a second MIM capacitor.
摘要翻译：实施例集成电路包括第一电容元件，其包括与第一电容元件并联耦合的第一金属氧化物半导体（MOS）电容器和第二电容元件，其中第二电容元件包括第二MOS电容器。此外，集成电路包括与第一电容元件和第二电容元件并联耦合的第三电容元件，其中第三电容元件包括第一金属 - 绝缘体金属（MIM）电容器和与第第一电容元件，第二电容元件和第三电容元件，其中第四电容元件包括第二MIM电容器。

25. 发明授权

US08907450B2 Metal-semiconductor wafer bonding for high-Q devices 有权
标题翻译：用于高Q器件的金属半导体晶片接合
公开(公告)号：US08907450B2
公开(公告)日：2014-12-09
申请号：US13293075
申请日：2011-11-09
申请人： Changhan Yun , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
发明人： Changhan Yun , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
IPC分类号： H01L29/92 , H01L21/02 , H01G4/12 , H01G4/33 , H01L49/02
CPC分类号： H01L29/66174 , H01G4/1272 , H01G4/33 , H01L28/40 , H01L28/75
摘要： Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.
摘要翻译：提供了用于高Q装置的金属半导体晶片接合的方法和装置。示例性电容器包括形成在玻璃基板，第二板和介电层上的第一板。在第一板和玻璃基板之间不使用有机粘合剂，并且电介质层可以是本征半导体。重掺杂的非本征半导体层接触电介质层。电介质和非本征半导体层夹在第一和第二板之间。在第一板和电介质层之间形成金属间层。金属间化合物层被热压接合到第一板和电介质层。电容器可以作为高Q电容器和/或变容二极管耦合在电路中，并且可以与移动设备集成。

26. 发明授权

US08860114B2 Structure and method for a fishbone differential capacitor 有权
标题翻译：鱼骨差分电容器的结构和方法
公开(公告)号：US08860114B2
公开(公告)日：2014-10-14
申请号：US13411052
申请日：2012-03-02
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L28/60 , H01L28/88 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor structure disposed on the substrate. The capacitor structure includes a first conductive component; a second conductive component and a third conductive component symmetrically configured on opposite sides of the first conductive component. The first, second and third conductive components are separated from each other by respective dielectric material.
摘要翻译：本发明提供集成电路。集成电路包括具有由第一轴线和垂直于第一轴线的第二轴线限定的表面的基板; 以及设置在基板上的电容器结构。电容器结构包括第一导电元件; 对称地配置在第一导电部件的相对侧上的第二导电部件和第三导电部件。第一，第二和第三导电部件通过相应的介电材料彼此分离。

27. 发明授权

US08835274B2 Interconnects and semiconductor devices including at least two portions of a metal nitride material and methods of fabrication 有权
标题翻译：包括金属氮化物材料的至少两部分和制造方法的互连和半导体器件
公开(公告)号：US08835274B2
公开(公告)日：2014-09-16
申请号：US14043536
申请日：2013-10-01
申请人： Micron Technology, Inc.
发明人： Yongjun Jeff Hu
IPC分类号： H01L29/92 , H01L29/94 , H01L21/74 , H01L49/02 , H01L27/108 , H01L21/768
CPC分类号： H01L29/945 , H01L21/743 , H01L21/76846 , H01L21/76847 , H01L27/10852 , H01L28/75 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal nitride material includes a different material than another portion. Interconnects including at least two portions of a metal nitride material are also disclosed, at least one of the portions of the metal nitride material are formed from a different material than another portion of the metal nitride material. Methods for fabricating such MIM capacitors and interconnects are also disclosed, as are semiconductor devices including such MIM capacitors and interconnects.
摘要翻译：金属 - 绝缘体 - 金属电容器，其具有包括金属氮化物材料的至少两部分的底部电极。金属氮化物材料的至少一部分包括与另一部分不同的材料。还公开了包括金属氮化物材料的至少两部分的互连件，金属氮化物材料的至少一部分由与金属氮化物材料的另一部分不同的材料形成。还公开了制造这种MIM电容器和互连的方法，以及包括这种MIM电容器和互连的半导体器件。

28. 发明授权

US08766403B2 Capacitor arrays for minimizing gradient effects and methods of forming the same 有权
标题翻译：用于最小化梯度效应的电容器阵列及其形成方法
公开(公告)号：US08766403B2
公开(公告)日：2014-07-01
申请号：US13366750
申请日：2012-02-06
申请人： Chi-Feng Huang , Chia-Chung Chen
发明人： Chi-Feng Huang , Chia-Chung Chen
IPC分类号： H01L29/92
CPC分类号： H01L27/0805 , H01L23/5223 , H01L27/016 , H01L27/0207 , H01L28/40 , H01L28/60 , H01L28/86 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having capacitor arrays and methods of forming the same. A semiconductor device is formed including a capacitor array. The capacitor array includes a plurality of operational capacitors formed along a diagonal of the capacitor array. The capacitor array also includes a plurality of dummy capacitors formed substantially symmetrically about the plurality of operational capacitors in the capacitor array. A first operational capacitor is formed at a first edge of the capacitor array. Each one of the plurality of operational capacitors is electrically coupled to a non-adjacent other one of the plurality of operational capacitors.
摘要翻译：具有电容器阵列的半导体器件及其形成方法。形成包括电容器阵列的半导体器件。电容器阵列包括沿着电容器阵列的对角线形成的多个工作电容器。电容器阵列还包括围绕电容器阵列中的多个工作电容器大致对称地形成的多个虚拟电容器。第一工作电容器形成在电容器阵列的第一边缘处。多个工作电容器中的每一个电耦合到多个工作电容器中的不相邻的另一个。

29. 发明申请

US20140118034A1 METHODS AND CIRCUITS FOR PROVIDING STABLE CURRENT AND VOLTAGE REFERENCES BASED ON CURRENTS FLOWING THROUGH ULTRA-THIN DIELECTRIC LAYER COMPONENTS 有权
标题翻译：基于通过超薄介质层组件流动的电流提供稳定电流和电压参考的方法和电路
公开(公告)号：US20140118034A1
公开(公告)日：2014-05-01
申请号：US13666916
申请日：2012-11-01
申请人： DUST NETWORKS, INC.
发明人： Mark Alan LEMKIN , Thor Nelson JUNEAU
IPC分类号： G05F3/02 , H03L5/02 , H01L29/92
CPC分类号： H03L5/02 , G05F3/24 , H01L29/94 , Y10S323/907
摘要： Low-power circuits for providing stable voltage and current references rely on currents flowing through ultra-thin dielectric layer components for operation. A current reference circuit includes driving circuitry operative to apply a voltage to the first terminal of the component with respect to the second terminal of the component in order to cause a current to flow through the dielectric layer, and sources a reference output current that is based on the current flow through the dielectric layer in response to the applied voltage. A voltage reference circuit includes a current source which applies a current to the ultra-thin dielectric layer component, and maintains an output node at a stable reference output voltage level based on the voltage across the ultra-thin dielectric layer component in response to the current flow through the dielectric layer.
摘要翻译：用于提供稳定电压和电流参考的低功率电路依赖于流过超薄介电层组件的电流进行操作。电流参考电路包括驱动电路，其可操作以相对于部件的第二端施加电压至元件的第一端，以使电流流过电介质层，并输出基于基准的参考输出电流通过响应于所施加的电压的电流流过电介质层。电压参考电路包括电流源，其将电流施加到超薄电介质层组件，并且基于超薄电介质层组件上的电压响应于电流而将输出节点维持在稳定的参考输出电压电平流过电介质层。

30. 发明申请

US20140117499A1 CAPACITOR AND SEMICONDUCTOR DEVICE USING SAME 有权
标题翻译：使用相同的电容器和半导体器件
公开(公告)号：US20140117499A1
公开(公告)日：2014-05-01
申请号：US14049269
申请日：2013-10-09
申请人： FITIPOWER INTEGRATED TECHNOLOGY, INC.
发明人： CHUN-PING YANG , DA-PONG ZHANG
IPC分类号： H01L29/92
CPC分类号： H01L29/92
摘要： A capacitor for a semiconductor device includes a bottom electrode plate, an insulating layer formed on the bottom electrode plate, and a top electrode plate formed on the insulating layer. The bottom plate includes a capacitor well and at least one diffused region formed on the capacitor well. A doping concentration of the at least one diffused region is higher than a doping concentration of the capacitor well, the capacitor well comprising a first well.
摘要翻译：用于半导体器件的电容器包括底电极板，形成在底电极板上的绝缘层和形成在绝缘层上的顶电极板。底板包括电容器阱和形成在电容器阱上的至少一个扩散区域。所述至少一个扩散区域的掺杂浓度高于电容器阱的掺杂浓度，所述电容器阱包括第一阱。

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