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1. 发明申请

US20120293191A1 HVMOS Reliability Evaluation using Bulk Resistances as Indices 有权
标题翻译：使用散装电阻作为指标的HVMOS可靠性评估
公开(公告)号：US20120293191A1
公开(公告)日：2012-11-22
申请号：US13111730
申请日：2011-05-19
申请人： Chia-Chung Chen , Chi-Feng Huang , Tse-Hua Lu
发明人： Chia-Chung Chen , Chi-Feng Huang , Tse-Hua Lu
IPC分类号： G01R27/08 , H01L27/105 , H01L21/66
CPC分类号： H01L27/092 , G01R27/08 , G01R31/02 , H01L22/14 , H01L22/34 , H01L27/0207 , H01L29/0619 , H01L29/0649 , H01L29/1087 , H01L29/7835
摘要： A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
摘要翻译：确定高压PMOS（HVPMOS）器件的可靠性的方法包括确定HVPMOS器件的体电阻，以及基于体电阻来评估HVPMOS器件的可靠性。

2. 发明授权

US09209098B2 HVMOS reliability evaluation using bulk resistances as indices 有权
标题翻译：使用体积电阻作为指标的HVMOS可靠性评估
公开(公告)号：US09209098B2
公开(公告)日：2015-12-08
申请号：US13111730
申请日：2011-05-19
申请人： Chia-Chung Chen , Chi-Feng Huang , Tse-Hua Lu
发明人： Chia-Chung Chen , Chi-Feng Huang , Tse-Hua Lu
IPC分类号： G01R27/08 , H01L21/66 , G01R31/02 , H01L29/78 , H01L29/10
CPC分类号： H01L27/092 , G01R27/08 , G01R31/02 , H01L22/14 , H01L22/34 , H01L27/0207 , H01L29/0619 , H01L29/0649 , H01L29/1087 , H01L29/7835
摘要： A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
摘要翻译：确定高压PMOS（HVPMOS）器件的可靠性的方法包括确定HVPMOS器件的体电阻，以及基于体电阻来评估HVPMOS器件的可靠性。

3. 发明授权

US09159802B2 MOS devices with mask layers and methods for forming the same 有权
标题翻译：具有掩模层的MOS器件及其形成方法
公开(公告)号：US09159802B2
公开(公告)日：2015-10-13
申请号：US13471270
申请日：2012-05-14
申请人： Chu-Fu Chen , Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang
发明人： Chu-Fu Chen , Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66
CPC分类号： H01L29/66492 , H01L21/28518 , H01L21/76897 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.
摘要翻译：器件包括衬底，衬底上的栅极电介质，以及栅极电介质上的栅电极。漏极区域和源极区域设置在栅电极的相对侧上。绝缘区域设置在基板中，其中绝缘区域的边缘与漏极区域和源极区域的边缘接触。介电掩模包括与漏极区域和绝缘区域的相邻部分之间的第一界面重叠的部分。漏极硅化物区域设置在漏极区域之上，其中硅化物区域的边缘基本上与电介质掩模的第一部分的边缘对准。

4. 发明授权

US08921978B2 Dual DNW isolation structure for reducing RF noise on high voltage semiconductor devices 有权
标题翻译：双DNW隔离结构，用于降低高压半导体器件的RF噪声
公开(公告)号：US08921978B2
公开(公告)日：2014-12-30
申请号：US13347031
申请日：2012-01-10
申请人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Hsiao-Chun Lee
发明人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Hsiao-Chun Lee
IPC分类号： H01L21/70
CPC分类号： H01L21/823892 , H01L21/761 , H01L27/0928
摘要： An isolation structure in a semiconductor device absorbs electronic noise and prevents substrate leakage currents from reaching other devices and signals. The isolation structure provides a duality of deep N-well (“DNW”) isolation structures surrounding an RF device or other source of electronic noise. The DNW isolation structures extend into the substrate at a depth of at least about 2.5 μm and may be coupled to VDD. P+ guard rings are also provided in some embodiments and are provided inside, outside or between the dual DNW isolation structures.
摘要翻译：半导体器件中的隔离结构吸收电子噪声并防止衬底漏电流到达其它器件和信号。隔离结构提供了围绕RF器件或其他电子噪声源的深N阱（“DNW”）隔离结构的二元性。 DNW隔离结构在至少约2.5μm的深度延伸到衬底中，并且可以耦合到VDD。在一些实施例中还提供了P +保护环，并且设置在双DNW隔离结构内部，外部或之间。

5. 发明申请

US20140001518A1 Integrated Circuit Devices with Well Regions and Methods for Forming the Same 审中-公开
标题翻译：具有井区的集成电路器件及其形成方法
公开(公告)号：US20140001518A1
公开(公告)日：2014-01-02
申请号：US13539027
申请日：2012-06-29
申请人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Mingo Liu
发明人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Mingo Liu
IPC分类号： H01L27/07 , H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/07 , H01L27/085 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/732 , H01L29/7327 , H01L29/808 , H01L29/861 , H01L29/93
摘要： A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.
摘要翻译：一种方法包括在衬底中形成第一导电类型的深阱区域，注入深阱区域的一部分以形成第一栅极，以及植入深阱区域以形成阱区域。阱区和第一栅极是与第一导电类型相反的第二导电类型。执行注入以在第一栅极上形成第一导电类型的沟道区。植入覆盖沟道区域的深阱区域的一部分以形成第二导电类型的第二栅极。进行源极/漏极注入以在第二栅极的相对侧上形成第一导电类型的源极区域和漏极区域。源极和漏极区域连接到沟道区域，并且与沟道区域和第一栅极重叠。

6. 发明申请

US20120104387A1 Four-Terminal Metal-Over-Metal Capacitor Design Kit 有权
标题翻译：四端子金属金属电容器设计套件
公开(公告)号：US20120104387A1
公开(公告)日：2012-05-03
申请号：US12915757
申请日：2010-10-29
申请人： Chia-Chung Chen , Chi-Feng Huang , Tse-Hua Lu , Sally Liu
发明人： Chia-Chung Chen , Chi-Feng Huang , Tse-Hua Lu , Sally Liu
IPC分类号： H01L23/544 , H01L29/92
CPC分类号： H01L23/5223 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A device includes a first MOM capacitor; a second MOM capacitor directly over and vertically overlapping the first MOM capacitor, wherein each of the first and the second MOM capacitors includes a plurality of parallel capacitor fingers; a first and a second port electrically coupled to the first MOM capacitor; and a third and a fourth port electrically coupled to the second MOM capacitor. The first, the second, the third, and the fourth ports are disposed at a surface of a respective wafer.
摘要翻译：一种器件包括第一MOM电容器; 第二MOM电容器直接在第一MOM电容器上方并垂直重叠，其中第一和第二MOM电容器中的每一个包括多个并联电容指; 电耦合到第一MOM电容器的第一和第二端口; 以及电耦合到第二MOM电容器的第三和第四端口。第一，第二，第三和第四端口设置在相应晶片的表面。

7. 发明授权

US10269658B2 Integrated circuit devices with well regions and methods for forming the same 有权
公开(公告)号：US10269658B2
公开(公告)日：2019-04-23
申请号：US13539027
申请日：2012-06-29
申请人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Mingo Liu
发明人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Mingo Liu
IPC分类号： H01L27/07 , H01L21/8249 , H01L27/06 , H01L27/085 , H01L29/732 , H01L29/808 , H01L29/861 , H01L29/93 , H01L29/06
摘要： A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

8. 发明申请

US20130299919A1 MOS Devices with Mask Layers and Methods for Forming the Same 有权
标题翻译：具有掩模层的MOS器件及其形成方法
公开(公告)号：US20130299919A1
公开(公告)日：2013-11-14
申请号：US13471270
申请日：2012-05-14
申请人： Chu-Fu Chen , Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang
发明人： Chu-Fu Chen , Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66492 , H01L21/28518 , H01L21/76897 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.
摘要翻译：器件包括衬底，衬底上的栅极电介质，以及栅极电介质上的栅电极。漏极区域和源极区域设置在栅电极的相对侧上。绝缘区域设置在基板中，其中绝缘区域的边缘与漏极区域和源极区域的边缘接触。介电掩模包括与漏极区域和绝缘区域的相邻部分之间的第一界面重叠的部分。漏极硅化物区域设置在漏极区域之上，其中硅化物区域的边缘基本上与电介质掩模的第一部分的边缘对准。

9. 发明授权

US08558228B2 Four-terminal metal-over-metal capacitor design kit 有权
标题翻译：四端子金属金属电容器设计套件
公开(公告)号：US08558228B2
公开(公告)日：2013-10-15
申请号：US12915757
申请日：2010-10-29
申请人： Chia-Chung Chen , Chi-Feng Huang , Tse-Hua Lu , Sally Liu
发明人： Chia-Chung Chen , Chi-Feng Huang , Tse-Hua Lu , Sally Liu
IPC分类号： H01L23/58
CPC分类号： H01L23/5223 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A device includes a first MOM capacitor; a second MOM capacitor directly over and vertically overlapping the first MOM capacitor, wherein each of the first and the second MOM capacitors includes a plurality of parallel capacitor fingers; a first and a second port electrically coupled to the first MOM capacitor; and a third and a fourth port electrically coupled to the second MOM capacitor. The first, the second, the third, and the fourth ports are disposed at a surface of a respective wafer.
摘要翻译：一种器件包括第一MOM电容器; 第二MOM电容器直接在第一MOM电容器上方并垂直重叠，其中第一和第二MOM电容器中的每一个包括多个并联电容指; 电耦合到第一MOM电容器的第一和第二端口; 以及电耦合到第二MOM电容器的第三和第四端口。第一，第二，第三和第四端口设置在相应晶片的表面。

10. 发明申请

US20120187494A1 MOS Varactor Structure and Methods 有权
标题翻译： MOS变容管结构与方法
公开(公告)号：US20120187494A1
公开(公告)日：2012-07-26
申请号：US13013677
申请日：2011-01-25
申请人： Chi-Feng Huang , Chia-Chung Chen
发明人： Chi-Feng Huang , Chia-Chung Chen
IPC分类号： H01L27/088 , H01L21/66
CPC分类号： H01L29/66174 , H01L27/0808 , H01L27/0811 , H01L29/93 , H01L29/94
摘要： Apparatus and methods for a MOS varactor structure are disclosed An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.
摘要翻译：公开了一种用于MOS可变电抗器结构的装置和方法。提供一种装置，包括限定在半导体衬底的一部分中的有源区; 在有源区域中延伸到半导体衬底中的掺杂阱区; 在所述掺杂阱区域上平行布置的至少两个栅极结构; 源极和漏极区域，设置在形成在栅极结构的相对侧上的阱区域中; 栅极连接器，形成在覆盖所述至少两个栅极结构并电耦合所述至少两个栅极结构的第一金属层中; 源极和漏极连接器，其形成在第二金属层中并电耦合到源极和漏极区域; 以及将第二金属层中的源极和漏极连接器与形成在第一金属层中的栅极连接器分开的层间电介质材料。公开了形成结构的方法。

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