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1. 发明授权

US08766403B2 Capacitor arrays for minimizing gradient effects and methods of forming the same 有权
标题翻译：用于最小化梯度效应的电容器阵列及其形成方法
公开(公告)号：US08766403B2
公开(公告)日：2014-07-01
申请号：US13366750
申请日：2012-02-06
申请人： Chi-Feng Huang , Chia-Chung Chen
发明人： Chi-Feng Huang , Chia-Chung Chen
IPC分类号： H01L29/92
CPC分类号： H01L27/0805 , H01L23/5223 , H01L27/016 , H01L27/0207 , H01L28/40 , H01L28/60 , H01L28/86 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having capacitor arrays and methods of forming the same. A semiconductor device is formed including a capacitor array. The capacitor array includes a plurality of operational capacitors formed along a diagonal of the capacitor array. The capacitor array also includes a plurality of dummy capacitors formed substantially symmetrically about the plurality of operational capacitors in the capacitor array. A first operational capacitor is formed at a first edge of the capacitor array. Each one of the plurality of operational capacitors is electrically coupled to a non-adjacent other one of the plurality of operational capacitors.
摘要翻译：具有电容器阵列的半导体器件及其形成方法。形成包括电容器阵列的半导体器件。电容器阵列包括沿着电容器阵列的对角线形成的多个工作电容器。电容器阵列还包括围绕电容器阵列中的多个工作电容器大致对称地形成的多个虚拟电容器。第一工作电容器形成在电容器阵列的第一边缘处。多个工作电容器中的每一个电耦合到多个工作电容器中的不相邻的另一个。

2. 发明申请

US20140158984A1 SEMICONDUCTOR STRUCTURE 审中-公开
标题翻译：半导体结构
公开(公告)号：US20140158984A1
公开(公告)日：2014-06-12
申请号：US13917645
申请日：2013-06-14
申请人： Chi-Feng Huang , Sheng-Han Tu
发明人： Chi-Feng Huang , Sheng-Han Tu
IPC分类号： H01L29/15
CPC分类号： H01L33/12 , H01L21/02381 , H01L21/02458 , H01L21/02505 , H01L21/0251 , H01L21/0254 , H01L29/2003 , H01L29/201 , H01L33/007 , H01L33/06 , H01L33/32
摘要： A semiconductor structure includes a silicon substrate, an aluminum nitride layer and a plurality of grading stress buffer layers. The aluminum nitride layer is disposed on the silicon substrate. The grading stress buffer layers are disposed on the aluminum nitride layer. Each grading stress buffer layer includes a grading layer and a transition layer stacked up sequentially. A chemical formula of the grading layer is Al1−xGaxN, wherein the x value is increased from one side near the silicon substrate to a side away from the silicon substrate, and 0≦x≦1. A chemical formula of the transition layer is the same as the chemical formula of a side surface of the grading layer away from the silicon substrate. The chemical formula of the transition layer of the grading stress buffer layer furthest from the silicon substrate is GaN.
摘要翻译：半导体结构包括硅衬底，氮化铝层和多个分级应力缓冲层。氮化铝层设置在硅衬底上。分级应力缓冲层设置在氮化铝层上。每个分级应力缓冲层包括依次层叠的分级层和过渡层。分级层的化学式为Al1-xGaxN，其中x值从硅衬底附近的一侧增加到远离硅衬底的一侧，并且0和n 1; x＆lt; 1; 1。过渡层的化学式与脱离硅衬底的分级层的侧表面的化学式相同。离硅衬底最远的分级应力缓冲层的过渡层的化学式为GaN。

3. 发明授权

US08450827B2 MOS varactor structure and methods 有权
标题翻译： MOS变容二极管的结构和方法
公开(公告)号：US08450827B2
公开(公告)日：2013-05-28
申请号：US13013677
申请日：2011-01-25
申请人： Chi-Feng Huang , Chia-Chung Chen
发明人： Chi-Feng Huang , Chia-Chung Chen
IPC分类号： H01L21/36
CPC分类号： H01L29/66174 , H01L27/0808 , H01L27/0811 , H01L29/93 , H01L29/94
摘要： Apparatus and methods for a MOS varactor structure are disclosed An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.
摘要翻译：公开了一种用于MOS可变电抗器结构的装置和方法。提供一种装置，包括限定在半导体衬底的一部分中的有源区; 在有源区域中延伸到半导体衬底中的掺杂阱区; 在所述掺杂阱区域上平行布置的至少两个栅极结构; 源极和漏极区域，设置在形成在栅极结构的相对侧上的阱区域中; 栅极连接器，形成在覆盖所述至少两个栅极结构并电耦合所述至少两个栅极结构的第一金属层中; 源极和漏极连接器，其形成在第二金属层中并电耦合到源极和漏极区域; 以及将第二金属层中的源极和漏极连接器与形成在第一金属层中的栅极连接器分开的层间电介质材料。公开了形成结构的方法。

4. 发明授权

US08186552B2 Stapler with leg-flatting and anvil-guiding capability 有权
标题翻译：订书机具有腿部平坦和砧导向能力
公开(公告)号：US08186552B2
公开(公告)日：2012-05-29
申请号：US12572621
申请日：2009-10-02
申请人： Chi-Feng Huang
发明人： Chi-Feng Huang
IPC分类号： B25C5/02
CPC分类号： B25C5/025 , B25C5/0207
摘要： A stapler has a supporting base, a magazine assembly, a trigger assembly, a leg-flatting device and a rail assembly. The magazine assembly and the trigger assembly are connected pivotally to the supporting base. The leg-flatting device is mounted on the supporting base and has a moving base and an anvil element. The moving base is connected operationally to the supporting base and has an anvil hole. The anvil element is mounted moveably in the anvil hole and has a functional segment and a non-functional segment. The rail assembly mounted on and protrudes from the bottom face of the supporting base and has at least one rail bracket protruding from the bottom face of the supporting base. Each one of the at least one rail bracket has a rail in which the non-functional segment of the anvil element is slidably mounted.
摘要翻译：订书机具有支撑底座，仓库组件，触发器组件，腿部平坦装置和导轨组件。刀库组件和扳机组件枢转地连接到支撑底座。腿部平坦装置安装在支撑基座上并具有移动基座和砧座元件。移动底座可操作地连接到支撑底座并具有砧孔。砧座元件可动地安装在砧孔中，并具有功能段和非功能段。所述轨道组件安装在所述支撑基座的底面上并从所述支撑基座的底面突出，并且具有从所述支撑基座的底面突出的至少一个轨道支架。所述至少一个轨道支架中的每一个具有轨道，其中所述砧元件的所述非功能段可滑动地安装在所述轨道中。

5. 发明申请

US20110043497A1 LED DISPLAY SYSTEM AND MODE-DETERMINING METHOD OF SAME 审中-公开
标题翻译： LED显示系统及其模式确定方法
公开(公告)号：US20110043497A1
公开(公告)日：2011-02-24
申请号：US12858596
申请日：2010-08-18
申请人： CHI-FENG HUANG
发明人： CHI-FENG HUANG
IPC分类号： G09G5/00
CPC分类号： G09G3/14 , G09G3/32 , G09G2310/0264 , G09G2310/0272 , G09G2370/08 , G09G2380/04
摘要： A LED display system includes a display controller including an output port having a first output terminal and a second output terminal; a plurality of LED sets; and a plurality of driving circuits, coupled in series and coupled between the display controller and the plurality of LED sets, respectively. Each of the driving circuits includes a first signal-input terminal, a first signal-output terminal, a second signal-input terminal, and a second signal-output terminal, wherein the first signal-input terminal of a first one of the driving circuits is coupled to the first output terminal, the second signal-input terminal of the first one of the driving circuits is coupled to the second output terminal. The display controller asserts a transition period for switching the driving circuits from a first operation mode to a second operation mode by manipulating a first signal outputted to the driving circuits through the first output terminal.
摘要翻译： LED显示系统包括：显示控制器，包括具有第一输出端和第二输出端的输出端; 多个LED组; 以及分别耦合在显示控制器和多个LED组之间的多个驱动电路。每个驱动电路包括第一信号输入端，第一信号输出端，第二信号输入端和第二信号输出端，其中第一驱动电路的第一信号输入端耦合到第一输出端，第一驱动电路的第二信号输入端耦合到第二输出端。显示控制器通过操作通过第一输出端子输出到驱动电路的第一信号来断言用于将驱动电路从第一操作模式切换到第二操作模式的转换周期。

6. 发明授权

US07875478B2 Method for controlling color contrast of a multi-wavelength light-emitting diode 失效
标题翻译：用于控制多波长发光二极管的色对比度的方法
公开(公告)号：US07875478B2
公开(公告)日：2011-01-25
申请号：US11819175
申请日：2007-06-26
申请人： Dong-Ming Yeh , Horng-Shyang Chen , Chih-Feng Lu , Chi-Feng Huang , Tsung-Yi Tang , Jian-Jang Huang , Yen-Cheng Lu , Chih-Chung Yang , Jeng-Jie Huang , Yung-Sheng Chen
发明人： Dong-Ming Yeh , Horng-Shyang Chen , Chih-Feng Lu , Chi-Feng Huang , Tsung-Yi Tang , Jian-Jang Huang , Yen-Cheng Lu , Chih-Chung Yang , Jeng-Jie Huang , Yung-Sheng Chen
IPC分类号： H01L21/00
CPC分类号： H01L33/06 , B82Y20/00 , H01L33/32
摘要： A method for controlling the color contrast of a multi-wavelength light-emitting diode (LED) made according to the present invention is disclosed. The present invention includes at least the step of increasing the junction temperature of a multi-quantum-well LED, such that holes are distributed in a deeper quantum-well layer of the LED to increase luminous intensity of the deeper quantum-well layer, thereby controlling the relative intensity ratios of the multiple wavelengths emitted by the LED. The step of increasing junction temperature of the multi-quantum-well LED is achieved either by controlling resistance through modulating thickness of a p-type electrode layer of the LED or by modifying the mesa area size to control its relative heat radiation surface area.
摘要翻译：公开了一种用于控制根据本发明制造的多波长发光二极管（LED）的颜色对比度的方法。本发明至少包括提高多量子阱LED的结温的步骤，使得空穴分布在LED的较深量子阱层中以增加较深量子阱层的发光强度，由此控制由LED发射的多个波长的相对强度比。通过调节LED的p型电极层的厚度或通过改变台面面积尺寸来控制其相对的热辐射表面积来实现增加多量子阱LED的结温的步骤。

7. 发明申请

US20100289519A1 CIRCUIT FOR DETECTING FAULTY DIODE 审中-公开
标题翻译：用于检测故障二极管的电路
公开(公告)号：US20100289519A1
公开(公告)日：2010-11-18
申请号：US12632126
申请日：2009-12-07
申请人： CHI-FENG HUANG
发明人： CHI-FENG HUANG
IPC分类号： G01R31/26 , G01R19/00
CPC分类号： G01R31/2635
摘要： A circuit for detecting faulty diode comprises a diode having an anode connected to a voltage supply; a resistor having a first end connected to a cathode of the diode; a transistor having a drain connected to a second end of the resistor and a source that is grounded; a differential amplifier having a positive terminal connected to the drain of the transistor, a negative terminal connected to a reference voltage input terminal for receiving a reference voltage, and an output terminal connected to a gate of the transistor; and a buffer having an input terminal connected to the gate of the transistor, and a signal output terminal used to output a faulty signal.
摘要翻译：用于检测故障二极管的电路包括具有连接到电压源的阳极的二极管; 电阻器，其具有连接到二极管的阴极的第一端; 具有连接到电阻器的第二端的漏极和接地的源极的晶体管; 具有连接到晶体管的漏极的正极端子的差分放大器，连接到用于接收参考电压的基准电压输入端子的负极端子和连接到晶体管的栅极的输出端子; 以及具有连接到晶体管的栅极的输入端的缓冲器和用于输出故障信号的信号输出端。

8. 发明申请

US20080299723A1 METHODS FOR FORMING CAPACITOR STRUCTURES 有权
标题翻译：形成电容器结构的方法
公开(公告)号：US20080299723A1
公开(公告)日：2008-12-04
申请号：US11757763
申请日：2007-06-04
申请人： C. C. Wu , Chi-Feng Huang , Chun-Hung Chen , Chih-Ping Chao , John Chern
发明人： C. C. Wu , Chi-Feng Huang , Chun-Hung Chen , Chih-Ping Chao , John Chern
IPC分类号： H01L21/82
CPC分类号： H01L27/0629 , H01L29/7833
摘要： A method for forming a capacitor includes forming a dielectric layer over a substrate. A conductive layer is formed over the dielectric layer. Dopants are implanted through at least one of the dielectric layer and the conductive layer after forming the dielectric layer so as to form a conductive region under the dielectric layer, wherein the conductive layer is a top electrode of the capacitor and the conductive region is a bottom electrode of the capacitor.
摘要翻译：形成电容器的方法包括在衬底上形成电介质层。在电介质层上形成导电层。在形成电介质层之后，通过介电层和导电层中的至少一个注入掺杂剂，以在电介质层下方形成导电区域，其中导电层是电容器的顶部电极，导电区域是底部电容器的电极。

9. 发明申请

US20080157056A1 Manufacturing method of poly-wavelength light-emitting diode of utilizing nano-crystals and the light-emitting device therefor 审中-公开
标题翻译：利用纳米晶体的多波长发光二极管的制造方法及其发光装置
公开(公告)号：US20080157056A1
公开(公告)日：2008-07-03
申请号：US11819169
申请日：2007-06-26
申请人： Dong-Ming Yeh , Horng-Shyang Chen , Chih-Feng Lu , Chi-Feng Huang , Wen-Yu Shiao , Jian-Jang Huang , Yen-Cheng Lu , Chih-Chung Yang
发明人： Dong-Ming Yeh , Horng-Shyang Chen , Chih-Feng Lu , Chi-Feng Huang , Wen-Yu Shiao , Jian-Jang Huang , Yen-Cheng Lu , Chih-Chung Yang
IPC分类号： H01L33/00
CPC分类号： H01L33/26 , H01L33/08 , H01L33/16
摘要： A producing method of poly-wavelength light-emitting diode of utilizing nano-crystals and the light-emitting device thereof includes growing and processing a multiple-quantum-well layer based on stacking the mixture of at least two kinds of quantum wells to produce a two-wavelength light-emitting diode. Then, attaching nano-crystals on the two-wavelength light-emitting diode to transfer one of the wavelengths of the two-wavelength light-emitting diode to produce a poly-wavelength light-emitting diode. The device of the present invention can emit blue, green and red lights to produce white light.
摘要翻译：利用纳米晶体的多波长发光二极管的制造方法及其发光装置包括：通过堆叠至少两种量子阱的混合物来生长和处理多量子阱层，以产生双波长发光二极管。然后，将纳米晶体附着在双波长发光二极管上，以传输双波长发光二极管的波长之一，以产生多波长发光二极管。本发明的装置可以发出蓝色，绿色和红色的光以产生白光。

10. 发明授权

US06734079B2 Microelectronic fabrication having sidewall passivated microelectronic capacitor structure fabricated therein 有权
标题翻译：具有在其中制造的侧壁钝化微电子电容器结构的微电子制造
公开(公告)号：US06734079B2
公开(公告)日：2004-05-11
申请号：US10170840
申请日：2002-06-13
申请人： Chi-Feng Huang , Shyh-Chyi Wang , Chih-Hsien Lin , Chun-Hon Chen , Tien-I Bao , Syun-Ming Jang
发明人： Chi-Feng Huang , Shyh-Chyi Wang , Chih-Hsien Lin , Chun-Hon Chen , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L2120
CPC分类号： H01L28/55 , Y10S438/945
摘要： Within a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is formed within the microelectronic fabrication a capacitor structure which comprises a first capacitor plate layer having formed thereupon a capacitor dielectric layer in turn having formed thereupon a second capacitor plate layer, wherein each of the foregoing layers having an exposed sidewall to thus form a series of exposed sidewalls. The capacitor structure also comprises a silicon oxide dielectric layer formed passivating the series of exposed sidewalls of the first capacitor plate layer, the capacitor dielectric layer and the second capacitor plate layer a silicon oxide dielectric layer.
摘要翻译：在制造微电子制造的方法和使用该方法制造的微电子制造中，在微电子制造中形成电容器结构，该电容器结构包括依次形成有电容器电介质层的第一电容器板层，其上形成有第二电容器板层，其中每个前述层具有暴露的侧壁，从而形成一系列暴露的侧壁。电容器结构还包括形成钝化第一电容器板层的一系列暴露的侧壁，电容器介电层和第二电容器板层的氧化硅介电层的氧化硅介电层。

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