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1. 发明申请

US20180374846A1 DUAL-SERIES VARACTOR EPI 审中-公开
公开(公告)号：US20180374846A1
公开(公告)日：2018-12-27
申请号：US16053211
申请日：2018-08-02
申请人： Qorvo US, Inc.
发明人： Peter V. Wright , Timothy S. Henderson
IPC分类号： H01L27/08 , H01L29/20
CPC分类号： H01L27/0808 , H01L25/07 , H01L29/20 , H01L29/2003 , H01L29/66174 , H01L29/66204 , H01L29/93 , H01L2224/48091 , H01L2924/00014 , H01L2924/0002 , H01L2924/00 , H01L2224/45099
摘要： A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.

2. 发明申请

US20180233605A1 TRANSCAP MANUFACTURING TECHNIQUES WITHOUT A SILICIDE-BLOCKING MASK 审中-公开
公开(公告)号：US20180233605A1
公开(公告)日：2018-08-16
申请号：US15850118
申请日：2017-12-21
申请人： QUALCOMM Incorporated
发明人： Fabio Alessio MARINO , Paolo MENEGOLI , Narasimhulu KANIKE , Francesco CAROBOLANTE , Qingqing LIANG
IPC分类号： H01L29/93 , H01L21/285 , H01L21/28 , H01L29/66 , H01L29/45 , H01L29/49
CPC分类号： H01L29/93 , H01L21/28052 , H01L21/28518 , H01L29/456 , H01L29/4933 , H01L29/66174 , H01L29/66189
摘要： Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a first non-insulative region disposed above a semiconductor region, and a second non-insulative region disposed adjacent to the semiconductor region. In certain aspects, the semiconductor variable capacitor also includes a first silicide layer disposed above the second non-insulative region, wherein the first silicide layer overlaps at least a portion of the semiconductor region. In certain aspects, a control region may be disposed adjacent to the semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

3. 发明申请

US20180233604A1 CMOS AND BIPOLAR DEVICE INTEGRATION INCLUDING A TUNABLE CAPACITOR 审中-公开
公开(公告)号：US20180233604A1
公开(公告)日：2018-08-16
申请号：US15431623
申请日：2017-02-13
申请人： QUALCOMM Incorporated
发明人： Shiqun GU , Gengming TAO , Richard HAMMOND , Ranadeep DUTTA , Matthew Michael NOWAK , Francesco CAROBOLANTE
IPC分类号： H01L29/93 , H01L29/20 , H01L29/22 , H01L29/47 , H01L29/737 , H01L29/66 , H01L27/06 , H01L21/822 , H01L23/00 , H01L23/66 , H03H11/34 , H03H11/04
CPC分类号： H01L29/93 , H01L21/8221 , H01L23/66 , H01L24/13 , H01L27/0629 , H01L27/0688 , H01L29/20 , H01L29/22 , H01L29/47 , H01L29/66174 , H01L29/66242 , H01L29/7371 , H01L2224/13025 , H03H11/04 , H03H11/342
摘要： A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

4. 发明授权

US09947701B2 Low noise device and method of forming the same 有权
公开(公告)号：US09947701B2
公开(公告)日：2018-04-17
申请号：US15428356
申请日：2017-02-09
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Victor Chiang Liang , Fu-Huan Tsai , Fang-Ting Kuo , Meng-Chang Ho , Yu-Lin Wei , Chi-Feng Huang
IPC分类号： H01L27/108 , H01L27/146 , H01L27/07 , H01L29/93
CPC分类号： H01L27/14603 , H01L27/0733 , H01L27/14614 , H01L27/1463 , H01L27/14689 , H01L29/66174 , H01L29/93
摘要： A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate. The gate stack includes a gate dielectric layer extending over a portion of the isolation feature, and a gate electrode over the gate dielectric layer. The low noise device further includes a charge trapping reducing structure adjacent to the isolation feature. The charge trapping reducing structure is configured to reduce a number of charge carriers adjacent an interface between the isolation feature and the channel.

5. 发明授权

US09882066B1 Transcap manufacturing techniques without a silicide-blocking mask 有权
公开(公告)号：US09882066B1
公开(公告)日：2018-01-30
申请号：US15429252
申请日：2017-02-10
申请人： QUALCOMM Incorporated
发明人： Fabio Alessio Marino , Paolo Menegoli , Narasimhulu Kanike , Francesco Carobolante , Qingqing Liang
IPC分类号： H01L29/93 , H01L29/45 , H01L29/49 , H01L21/285 , H01L21/28 , H01L29/66
CPC分类号： H01L29/93 , H01L21/28052 , H01L21/28518 , H01L29/456 , H01L29/4933 , H01L29/66174 , H01L29/66189
摘要： Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a first non-insulative region disposed above a semiconductor region, and a second non-insulative region disposed adjacent to the semiconductor region. In certain aspects, the semiconductor variable capacitor also includes a first silicide layer disposed above the second non-insulative region, wherein the first silicide layer overlaps at least a portion of the semiconductor region. In certain aspects, a control region may be disposed adjacent to the semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

6. 发明授权

US09829507B2 Method of manufacturing semiconductor device, and probe card 有权
公开(公告)号：US09829507B2
公开(公告)日：2017-11-28
申请号：US15045952
申请日：2016-02-17
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Takashi Saito
IPC分类号： G01R31/302 , G01R1/067 , G01R1/073 , G01R27/08 , G01R31/28 , H01L29/66 , H01L29/93
CPC分类号： G01R1/0675 , G01R1/07342 , G01R27/08 , G01R31/2889 , H01L29/66174 , H01L29/93
摘要： Reliability of an electrical test of a semiconductor wafer is improved. A method of manufacturing a semiconductor device includes a step of performing an electrical test of a semiconductor element by allowing contact portions (tips) of a force terminal (contact terminal) and a sense terminal (contact terminal) held by a probe card (first card) to come into contact with an electrode terminal of a semiconductor wafer. In the step of performing the electrical test, the contact portions of the force terminal and the sense terminal move in a direction away from each other after coming into contact with the first electrode terminal.

7. 发明授权

US09721946B2 Backside coupled symmetric varactor structure 有权
公开(公告)号：US09721946B2
公开(公告)日：2017-08-01
申请号：US15298124
申请日：2016-10-19
申请人： QUALCOMM Incorporated
发明人： Daeik Daniel Kim , David Francis Berdy , Je-Hsiung Jeffrey Lan , Changhan Hobie Yun , Jonghae Kim
IPC分类号： H01L29/93 , H01L27/108 , H01L21/70 , H01L21/8238 , H01L27/08 , H01L29/66 , H01L21/762 , H01L27/12 , H01L21/78
CPC分类号： H01L27/0808 , H01L21/7624 , H01L21/76264 , H01L21/78 , H01L27/1203 , H01L29/66174 , H01L29/66181 , H01L29/93
摘要： A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.

8. 发明申请

US20170125610A1 SEMICONDUCTOR STRUCTURE INCLUDING A VARACTOR 有权
公开(公告)号：US20170125610A1
公开(公告)日：2017-05-04
申请号：US14928595
申请日：2015-10-30
申请人： GLOBALFOUNDRIES Inc.
发明人： Alexandru Romanescu , Christian Schippel , Nicolas Sassiat
IPC分类号： H01L29/93 , H01L29/66 , H01L29/49 , H01L27/06 , H01L29/161 , H01L29/10
CPC分类号： H01L29/93 , H01L27/0629 , H01L29/1054 , H01L29/1095 , H01L29/161 , H01L29/4966 , H01L29/66174 , H01L29/66537 , H01L29/6659
摘要： A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.

9. 发明申请

US20160365427A1 COMPOUND VARACTOR 有权
标题翻译：化合物VARACTOR
公开(公告)号：US20160365427A1
公开(公告)日：2016-12-15
申请号：US15245468
申请日：2016-08-24
申请人： Qorvo US, Inc.
发明人： Peter V. Wright
IPC分类号： H01L29/66
CPC分类号： H01L29/66174 , H01L27/0808 , H01L29/6609 , H01L29/66121 , H01L29/66128 , H01L29/861 , H01L29/93
摘要： The present disclosure provides a method for fabricating a compound varactor. The method includes steps of depositing a collector layer, depositing a first base layer arranged in a first plurality of parallel fingers directly onto the collector layer, and depositing a second base layer arranged in a second plurality of parallel fingers that are interleaved with the first plurality of parallel fingers directly onto the collector layer.
摘要翻译：本公开提供了一种制造复合变容二极管的方法。该方法包括以下步骤：沉积集电极层，将布置在第一多个平行指状物中的第一基底层直接沉积到集电极层上，以及沉积布置在第二多个平行指状物中的第二基底层，该第二基底层与第一多个平行手指直接放置在收集层上。

10. 发明申请

US20160133758A1 DUAL STACK VARACTOR 审中-公开
标题翻译：双堆叠变送器
公开(公告)号：US20160133758A1
公开(公告)日：2016-05-12
申请号：US14995329
申请日：2016-01-14
申请人： TriQuint Semiconductor, Inc.
发明人： Peter V. Wright
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L27/0808 , H01L29/20 , H01L29/2003 , H01L29/66174
摘要： Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common and may be electrically coupled to form a parallel varactor pair. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common. The parallel varactor pair may be advantageous in reducing die area for compound varactor circuits.
摘要翻译：实施例包括与垂直堆叠的变容二极管相关的装置和方法。特别地，两个变容二极管可以由包括阳极层，接触层和变容二极管层的垂直堆叠层构成。两个变容二极管可以共用一个或多个层，并且可以电耦合以形成平行的变容二极管对。在一些实施例中，两个变容二极管可以共用共用阳极层，而在其它实施例中，两个变容二极管共同共用接触层。平行变容二极管对可以有利于减小复合变容二极管电路的管芯面积。

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