专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20050093047A1 Semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20050093047A1
公开(公告)日：2005-05-05
申请号：US10954238
申请日：2004-10-01
申请人： Akira Goda , Mitsuhiro Noguchi
发明人： Akira Goda , Mitsuhiro Noguchi
IPC分类号： H01L21/8247 , H01L21/8246 , H01L27/00 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are formed to be deep in the high voltage transistor region of the peripheral circuit region, in particular in a high voltage transistor region thereof, in order to improve the element isolation withstand voltage. A plurality of memory cell transistors having an ONO layer 15 serving as a charge accumulating insulating layer are provided in the memory cell region, where element isolation grooves 6 for these memory cell transistors are narrow and shallow. Two types of transistors, one for high voltage and the other for low voltage, having gate insulating layers 16 or 17, which are different from the ONO layer 15 in the memory cell region, are provided in the peripheral circuit region, where at least element isolation grooves 23 for high voltage transistors are wide and deep. In this way, it is possible to improve the degree of integration and yield in the memory cell region, and secure withstand voltage in the peripheral circuit region.
摘要翻译：提出了具有存储单元区域和外围电路区域的半导体存储器件以及制造这种半导体存储器件的方法，其中沟槽形成在存储单元区域中较浅以提高产量，并且在周边电路区域的高电压晶体管区域，特别是在其高压晶体管区域中形成深沟槽，以便提高元件隔离耐受电压。在存储单元区域中设置有多个具有作为电荷累积绝缘层的ONO层15的存储单元晶体管，其中用于这些存储单元晶体管的元件隔离槽6窄而浅。在外围电路区域中设置两个类型的晶体管，一个用于高电压，另一个用于低电压，具有与存储单元区域中的ONO层15不同的栅极绝缘层16或17，其中至少元件用于高压晶体管的隔离槽23宽而深。以这种方式，可以提高存储单元区域的集成度和产量，并且确保外围电路区域中的耐受电压。

32. 发明申请

US20050045941A1 Nonvolatile semiconductor memory and method of fabricating the same 审中-公开
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20050045941A1
公开(公告)日：2005-03-03
申请号：US10893295
申请日：2004-07-19
申请人： Koichi Kurita , Mitsuhiro Noguchi , Akira Goda
发明人： Koichi Kurita , Mitsuhiro Noguchi , Akira Goda
IPC分类号： G11C17/00 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： According to the present invention, there is provided a nonvolatile semiconductor memory capable of electrically writing and erasing information, comprising: a semiconductor substrate; source and drain regions formed at a predetermined spacing in a surface portion of said semiconductor substrate; a channel region positioned between said source and drain regions; a floating gate electrode formed on said cannel region via a first insulating film; a control gate electrode including a semiconductor layer formed on said floating gate electrode via a second insulating film, and a metal layer formed on said semiconductor layer; and an oxidation-resistant third insulating film formed on said control gate electrode, wherein the nonvolatile semiconductor memory further comprises an oxidation-resistant fourth insulating film so formed as to cover at least sidewalls of said metal layer, and said fourth insulating film is formed from the sidewalls of said metal layer to at least portions of sidewalls of said semiconductor layer of said control gate electrode.
摘要翻译：根据本发明，提供一种能够电写入和擦除信息的非易失性半导体存储器，包括：半导体衬底; 在所述半导体衬底的表面部分中以预定间隔形成的源区和漏区; 位于所述源区和漏区之间的沟道区; 经由第一绝缘膜形成在所述槽区上的浮栅电极; 包括经由第二绝缘膜形成在所述浮置栅电极上的半导体层的控制栅电极和形成在所述半导体层上的金属层; 以及形成在所述控制栅电极上的抗氧化的第三绝缘膜，其中所述非易失性半导体存储器还包括形成为至少覆盖所述金属层的侧壁的耐氧化的第四绝缘膜，并且所述第四绝缘膜由所述金属层的侧壁至所述控制栅电极的所述半导体层的侧壁的至少部分。

33. 发明申请

US20050018485A1 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：US20050018485A1
公开(公告)日：2005-01-27
申请号：US10920355
申请日：2004-08-18
申请人： Mitsuhiro Noguchi , Akira Goda , Yasuhiko Matsunaga
发明人： Mitsuhiro Noguchi , Akira Goda , Yasuhiko Matsunaga
IPC分类号： G11C16/06 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/26 , G11C16/0483 , H01L27/115
摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.
摘要翻译：一种包括存储单元单元的半导体存储器，所述存储单元单元包括：多个存储单元，其中当前端子之间的每个电导根据保持的数据而改变，每个存储单元具有串联连接在第一端子和第二端子之间的多个电流端子终端，并且每个都能够电气地重写数据; 将所述第一端子电连接到数据传输线路的第一选择开关元件; 以及用作将所述第二端子连接到参考电位线的第二选择开关元件的MISFET，其中所述半导体存储器具有用于将所述存储单元单元的第一和第二选择开关元件强制为导通的数据读取模式，施加读取电压用于根据所选择的存储单元的数据将当前端子之间的路径强制为导通或截止，到所选存储单元的控制电极，施加通过电压，以迫使当前端子之间的路径导通，而不管除了所述选择的存储单元之外的每个存储单元的数据，还包括除了所选择的存储单元之外的每个存储单元的控制电极，以及检测所述数据传输线与所述参考电压之间的电流的存在和否定电位线，并且在所述数据读取模式中，将所述MISFET的电流端子之间的电导设置为低于电导，关于当前终端之间的电导被设置为最低的情况，关于除了所选择的存储单元之外的至少一个存储单元。

34. 发明授权

US06828624B1 Nonvolatile semiconductor memory device covered with insulating film which is hard for an oxidizing agent to pass therethrough 失效
标题翻译：被绝缘膜覆盖的非易失性半导体存储器件，其难以氧化剂通过
公开(公告)号：US06828624B1
公开(公告)日：2004-12-07
申请号：US09556777
申请日：2000-04-25
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L29792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A nonvolatile semiconductor memory device includes comprises: an element isolation region being in contact with a first element region, an insulating film covering a memory cell, a peripheral transistor and the element isolation region, an inter-level insulating film provided on the surface of the insulating film, and a contact hole provided in the inter-level insulating film and the insulating film. The inter-level insulating film contains an insulator different from the insulating film. The contact hole reaches at least one of source and drain diffusion layers of the memory cell and overlaps the element isolation region. The insulating film contains an insulator different from the element isolation region and the insulating film is harder for an oxidizing agent to pass therethrough than a silicon oxide film. A surface of the insulating film is oxidized.
摘要翻译：非易失性半导体存储器件包括：与第一元件区域接触的元件隔离区域，覆盖存储单元的绝缘膜，外围晶体管和元件隔离区域，设置在第一元件区域的表面上的层间绝缘膜绝缘膜和设置在层间绝缘膜和绝缘膜中的接触孔。层间绝缘膜含有与绝缘膜不同的绝缘体。接触孔到达存储单元的源极和漏极扩散层中的至少一个并且与元件隔离区域重叠。绝缘膜含有与元件隔离区不同的绝缘体，绝缘膜比氧化硅膜更难以通过氧化剂。绝缘膜的表面被氧化。

35. 发明授权

US09171626B2 Memory devices and programming memory arrays thereof 有权
标题翻译：存储器件及其编程存储器阵列
公开(公告)号：US09171626B2
公开(公告)日：2015-10-27
申请号：US13561637
申请日：2012-07-30
申请人： Akira Goda , Haitao Liu , Krishna Parat
发明人： Akira Goda , Haitao Liu , Krishna Parat
IPC分类号： G11C16/04 , G11C16/10 , H01L27/115
CPC分类号： G11C16/10 , G11C16/0483 , H01L27/11556 , H01L27/11582
摘要： An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.
摘要翻译：一种方法的实施例包括在第一选择栅极截止时减小施加到第一选择栅极的电压减去施加到源极的电压的差异，减小施加到第二选择栅极的电压的差减去施加到数据线，而第二选择栅极关闭，以及增加施加到所选择的存取线的信号的电压，该选择的存取线耦合到耦合到第一和第二选择栅极的一串存储单元中的非目标存储器单元到编程电压之后或基本同时地减小施加到第一选择栅极的电压的差减去施加到源极的电压，并且减小施加到第二选择栅极的电压的差减去施加到数据线的电压。

36. 发明授权

US08787090B2 Memory cell operation 有权
标题翻译：存储单元操作
公开(公告)号：US08787090B2
公开(公告)日：2014-07-22
申请号：US13372669
申请日：2012-02-14
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C16/3468
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.
摘要翻译：本公开的实施例提供用于编程存储器单元的方法，设备，模块和系统。一种方法包括确定用于将阵列的一组存储器单元放置在擦除状态中的擦除脉冲的量，以及至少部分地基于确定的擦除量来调整与编程存储器单元组相关联的至少一个操作参数脉冲。

37. 发明授权

US08750040B2 Memory devices having source lines directly coupled to body regions and methods 有权
标题翻译：具有直接耦合到身体区域的源极线的存储器件和方法
公开(公告)号：US08750040B2
公开(公告)日：2014-06-10
申请号：US13011223
申请日：2011-01-21
申请人： Akira Goda
发明人： Akira Goda
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , H01L27/11524 , H01L27/11556
摘要： Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.
摘要翻译：显示了存储器件，存储器单元串和操作存储器件的方法。所描述的配置包括将细长体区直接耦合到源线。显示的配置和方法应为存储器操作（如擦除）提供可靠的身体区域偏置。

38. 发明授权

US08681562B2 Memories and methods of programming memories 有权
标题翻译：记忆和程序记忆的方法
公开(公告)号：US08681562B2
公开(公告)日：2014-03-25
申请号：US13051599
申请日：2011-03-18
申请人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
发明人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C16/3459
摘要： Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution.
摘要翻译：公开了用于调整存储器上部页面编程的装置和方法。在至少一个实施例中，在用于较低页编程的单个编程脉冲之后确定阈值电压分布上限，并且基于所确定的阈值电压分布的上限来调整上页编程开始电压。

39. 发明申请

US20140029345A1 MEMORY DEVICES AND PROGRAMMING MEMORY ARRAYS THEREOF 有权
标题翻译：存储器件和编程存储器阵列
公开(公告)号：US20140029345A1
公开(公告)日：2014-01-30
申请号：US13561637
申请日：2012-07-30
申请人： Akira Goda , Haitao Liu , Krishna Parat
发明人： Akira Goda , Haitao Liu , Krishna Parat
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , H01L27/11556 , H01L27/11582
摘要： An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.
摘要翻译：一种方法的实施例包括在第一选择栅极截止时减小施加到第一选择栅极的电压减去施加到源极的电压的差异，减小施加到第二选择栅极的电压的差减去施加到数据线，而第二选择栅极关闭，以及增加施加到所选择的存取线的信号的电压，该选择的存取线耦合到耦合到第一和第二选择栅极的一串存储单元中的非目标存储器单元到编程电压之后或基本同时地减小施加到第一选择栅极的电压的差减去施加到源极的电压，并且减小施加到第二选择栅极的电压的差减去施加到数据线的电压。

40. 发明授权

US08634252B2 Methods of operating a memory device having a buried boosting plate 有权
标题翻译：操作具有埋地升压板的存储器件的方法
公开(公告)号：US08634252B2
公开(公告)日：2014-01-21
申请号：US13351148
申请日：2012-01-16
申请人： Akira Goda
发明人： Akira Goda
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , H01L21/84 , H01L27/11526 , H01L27/11529 , H01L27/1203
摘要： Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed.
摘要翻译：公开了存储器件，例如包括具有升压板的绝缘体上半导体（SOI）NAND存储器阵列的存储器件。升压板可以设置在SOI衬底的绝缘体层中，使得升压板对存储器阵列的p阱施加电容耦合效应。这种升压板可用于在存储器阵列的编程和擦除操作期间升压p阱。在读取操作期间，升压板可以接地以最小化与p阱的相互作用。还公开了包括存储器阵列的系统和操作存储器阵列的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式