专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09171626B2 Memory devices and programming memory arrays thereof 有权
标题翻译：存储器件及其编程存储器阵列
公开(公告)号：US09171626B2
公开(公告)日：2015-10-27
申请号：US13561637
申请日：2012-07-30
申请人： Akira Goda , Haitao Liu , Krishna Parat
发明人： Akira Goda , Haitao Liu , Krishna Parat
IPC分类号： G11C16/04 , G11C16/10 , H01L27/115
CPC分类号： G11C16/10 , G11C16/0483 , H01L27/11556 , H01L27/11582
摘要： An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.
摘要翻译：一种方法的实施例包括在第一选择栅极截止时减小施加到第一选择栅极的电压减去施加到源极的电压的差异，减小施加到第二选择栅极的电压的差减去施加到数据线，而第二选择栅极关闭，以及增加施加到所选择的存取线的信号的电压，该选择的存取线耦合到耦合到第一和第二选择栅极的一串存储单元中的非目标存储器单元到编程电压之后或基本同时地减小施加到第一选择栅极的电压的差减去施加到源极的电压，并且减小施加到第二选择栅极的电压的差减去施加到数据线的电压。

2. 发明申请

US20140029345A1 MEMORY DEVICES AND PROGRAMMING MEMORY ARRAYS THEREOF 有权
标题翻译：存储器件和编程存储器阵列
公开(公告)号：US20140029345A1
公开(公告)日：2014-01-30
申请号：US13561637
申请日：2012-07-30
申请人： Akira Goda , Haitao Liu , Krishna Parat
发明人： Akira Goda , Haitao Liu , Krishna Parat
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , H01L27/11556 , H01L27/11582
摘要： An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.
摘要翻译：一种方法的实施例包括在第一选择栅极截止时减小施加到第一选择栅极的电压减去施加到源极的电压的差异，减小施加到第二选择栅极的电压的差减去施加到数据线，而第二选择栅极关闭，以及增加施加到所选择的存取线的信号的电压，该选择的存取线耦合到耦合到第一和第二选择栅极的一串存储单元中的非目标存储器单元到编程电压之后或基本同时地减小施加到第一选择栅极的电压的差减去施加到源极的电压，并且减小施加到第二选择栅极的电压的差减去施加到数据线的电压。

3. 发明申请

US20130258781A1 MEMORY DEVICES AND BIASING METHODS FOR MEMORY DEVICES 有权
标题翻译：用于存储器件的存储器件和偏置方法
公开(公告)号：US20130258781A1
公开(公告)日：2013-10-03
申请号：US13438331
申请日：2012-04-03
申请人： Akira Goda , Yijie Zhao , Krishna Parat
发明人： Akira Goda , Yijie Zhao , Krishna Parat
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source where the data line and the source are biased to substantially the same potential during a programming and/or erase operation performed on one or more of the strings of memory cells.
摘要翻译：存储器件中的偏置的装置，系统和方法促进存储器件编程和/或擦除操作。在至少一个实施例中，包括所选择的存储器单元和第二存储单元串的存储器单元的第一串被耦合到公共数据线和公共源，其中数据线和源被偏置到基本上相同的电位对一个或多个存储器单元串执行编程和/或擦除操作。

4. 发明授权

US08498159B2 Independent well bias management in a memory device 有权
标题翻译：存储器件中的独立阱偏置管理
公开(公告)号：US08498159B2
公开(公告)日：2013-07-30
申请号：US13465328
申请日：2012-05-07
申请人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
发明人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483
摘要： Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.
摘要翻译：提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。

5. 发明授权

US08331160B2 Memory device having improved programming operation 有权
标题翻译：存储器件具有改进的编程操作
公开(公告)号：US08331160B2
公开(公告)日：2012-12-11
申请号：US13193192
申请日：2011-07-28
申请人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
发明人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/0483 , G11C16/10 , G11C16/32
摘要： Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
摘要翻译：一些实施例包括具有模块和存储器单元的方法和装置。该模块被配置为在编程操作期间减少存储器单元的源极和漏极中的电子量。

6. 发明申请

US20120218824A1 INDEPENDENT WELL BIAS MANAGEMENT IN A MEMORY DEVICE 有权
标题翻译：在存储设备中独立的良好BIAS管理
公开(公告)号：US20120218824A1
公开(公告)日：2012-08-30
申请号：US13465328
申请日：2012-05-07
申请人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
发明人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.
摘要翻译：提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。

7. 发明授权

US08174893B2 Independent well bias management in a memory device 有权
标题翻译：存储器件中的独立阱偏置管理
公开(公告)号：US08174893B2
公开(公告)日：2012-05-08
申请号：US12582458
申请日：2009-10-20
申请人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
发明人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483
摘要： Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.
摘要翻译：提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。

8. 发明授权

US09251907B2 Memory devices and methods of operating memory devices including applying a potential to a source and a select gate between the source and a string of memory cells while performing a program operation on a memory cell in the string 有权
标题翻译：存储器件和操作存储器件的方法包括在源和存储器单元串之间向源和选择栅极施加电位，同时对字符串中的存储器单元执行编程操作
公开(公告)号：US09251907B2
公开(公告)日：2016-02-02
申请号：US13438331
申请日：2012-04-03
申请人： Akira Goda , Yijie Zhao , Krishna Parat
发明人： Akira Goda , Yijie Zhao , Krishna Parat
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source where the data line and the source are biased to substantially the same potential during a programming and/or erase operation performed on one or more of the strings of memory cells.
摘要翻译：存储器件中的偏置的装置，系统和方法促进存储器件编程和/或擦除操作。在至少一个实施例中，包括所选择的存储器单元和第二存储单元串的存储器单元的第一串被耦合到公共数据线和公共源，其中数据线和源被偏置到基本上相同的电位对一个或多个存储器单元串执行编程和/或擦除操作。

9. 发明申请

US20130016569A1 MEMORY DEVICE HAVING IMPROVED PROGRAMMING OPERATION 有权
标题翻译：具有改进的编程操作的存储器件
公开(公告)号：US20130016569A1
公开(公告)日：2013-01-17
申请号：US13621052
申请日：2012-09-15
申请人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
发明人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/3404 , G11C16/0483 , G11C16/10 , G11C16/32
摘要： Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
摘要翻译：一些实施例包括具有模块和存储器单元的方法和装置。该模块被配置为在编程操作期间减少存储器单元的源极和漏极中的电子量。

10. 发明申请

US20110280085A1 MEMORY DEVICE HAVING IMPROVED PROGRAMMING OPERATION 有权
标题翻译：具有改进的编程操作的存储器件
公开(公告)号：US20110280085A1
公开(公告)日：2011-11-17
申请号：US13193192
申请日：2011-07-28
申请人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
发明人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/3404 , G11C16/0483 , G11C16/10 , G11C16/32
摘要： Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
摘要翻译：一些实施例包括具有模块和存储器单元的方法和装置。该模块被配置为在编程操作期间减少存储器单元的源极和漏极中的电子量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式