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31. 再颁专利

USRE38821E1 Switching ethernet controller 有权
标题翻译：切换以太网控制器
公开(公告)号：USRE38821E1
公开(公告)日：2005-10-11
申请号：US09903808
申请日：2001-07-12
申请人： David Shemla , Avigdor Willenz
发明人： David Shemla , Avigdor Willenz
IPC分类号： H04L12/28 , H04L12/931 , H04L12/935 , H04L12/937
CPC分类号： H04L49/254 , H04L49/201 , H04L49/3009 , H04L49/3018 , H04L49/351
摘要： An Ethernet controller, for use within an Ethernet network of other Ethernet controller connected together by a bus, is provided. The Ethernet controller includes a plurality of ports including at least one bus port associated with ports connected to other switching Ethernet controllers, a hash table for storing addresses of ports within the Ethernet network, a hash table address control, a storage buffer including a multiplicity of contiguous buffers in which to temporarily store said packet, an empty list including a multiplicity of single bit buffers, a packet storage manager, a packet transfer manager and a write-only bus communication unit. The hash table address control hashes the address of a packet to initial hash table location values, changes the hash table location values by a fixed jump amount if the address values stored in the initial hash table location do not match the received address, and provides at least an output port number of the port associated with the received address. The packet storage manager associates the state of the bit of a single bit buffer with the empty or full state of an associated contiguous buffer and generates the address of a contiguous buffer. The packet transfer manager directs the temporarily stored packet to the port determined by said hash table control unit. The write-only bus communication unit is activated by the packet transfer manager, for transferring the packet out of the bus port by utilizing the bus for write only operations.
摘要翻译：提供了一种以太网控制器，用于通过总线连接在一起的其他以太网控制器的以太网网络内。以太网控制器包括多个端口，其包括与连接到其他交换以太网控制器的端口相关联的至少一个总线端口，用于存储以太网内的端口的地址的散列表，散列表地址控制，包括多个临时存储所述分组的连续缓冲器，包括多个单个位缓冲器的空列表，分组存储管理器，分组传送管理器和只写总线通信单元。哈希表地址控制将数据包的地址散列到初始哈希表位置值，如果存储在初始哈希表位置的地址值与接收到的地址不匹配，则将哈希表位置值更改为固定跳转量，并提供至少与接收到的地址相关联的端口的输出端口号。分组存储管理器将单个位缓冲器的位的状态与相关联的连续缓冲器的空或完全状态相关联，并且生成连续缓冲器的地址。分组传送管理器将临时存储的分组引导到由所述哈希表控制单元确定的端口。只写总线通信单元被分组传送管理器激活，用于通过利用用于仅写操作的总线将数据包传出总线端口。

32. 发明申请

US20050041579A1 Head of line blocking 审中-公开
标题翻译：线阻塞
公开(公告)号：US20050041579A1
公开(公告)日：2005-02-24
申请号：US10876653
申请日：2004-06-28
申请人： Eitan Medina , David Shemla , Yosi Solt
发明人： Eitan Medina , David Shemla , Yosi Solt
IPC分类号： H04J3/14 , H04L12/931 , H04L12/935
CPC分类号： H04L49/508 , H04L49/201 , H04L49/30 , H04L49/501
摘要： A network switch which includes a plurality of output ports, at least one input port and a queuing manager. Each output port has a control unit associated therewith. The input port receives incoming data destined for various ones of the output ports. The queuing manager directs the incoming data to their destination output ports. Each control unit includes an output queue, a fullness/emptiness sensor and a head of line (HOL) mask. The output queue stores the incoming data destined for its associated output port. The sensor senses when the output queue reaches a fullness or an emptiness state. The HOL mask is connected to the output of the sensor and blocks inflow of the incoming data to the output queue when the sensor senses the fullness state and for enabling inflow when the sensor senses the emptiness state.
摘要翻译：一种网络交换机，包括多个输出端口，至少一个输入端口和排队管理器。每个输出端口具有与其相关联的控制单元。输入端口接收去往各种输出端口的输入数据。排队管理器将传入的数据引导到其目标输出端口。每个控制单元包括输出队列，丰满度/空虚传感器和行头（HOL）掩模。输出队列存储发往其相关输出端口的输入数据。传感器检测输出队列何时达到饱和或空虚状态。当传感器感测到充满状态并且当传感器感测到空虚状态时，HOL掩模连接到传感器的输出并阻止输入数据流入输出队列。

33. 发明申请

US20050005037A1 Buffer switch having descriptor cache and method thereof 失效
标题翻译：具有描述符缓存的缓冲器开关及其方法
公开(公告)号：US20050005037A1
公开(公告)日：2005-01-06
申请号：US10835270
申请日：2004-04-28
申请人： David Shemla , Rami Rozensvaig
发明人： David Shemla , Rami Rozensvaig
IPC分类号： H04L12/861 , H04L12/879 , H04L12/935 , G06F13/14
CPC分类号： H04L49/901 , H04L49/3036 , H04L49/90
摘要： A device for writing descriptors, the device including a local memory comprising a multiplicity of mini-queues, wherein each of the mini-queues temporarily stores a plurality of descriptors, wherein each of the descriptors is associated with one of the data packets. Additionally including an output memory comprising a multiplicity of output queues, wherein each of the output queues in output memory is associated with one of the queues in said local memory, and a burst writer which writes N descriptors simultaneously from the mini-queue in the local memory to its associated output queue in output memory.
摘要翻译：一种用于写入描述符的设备，所述设备包括包括多个小型队列的本地存储器，其中每个所述小型队列临时存储多个描述符，其中每个描述符与所述数据分组之一相关联。另外包括包括多个输出队列的输出存储器，其中输出存储器中的每个输出队列与所述本地存储器中的一个队列相关联，以及突发写入器，其从本地的小型队列同时写入N个描述符内存到输出内存中的相关输出队列。

34. 发明授权

US06738838B2 Network switch having descriptor cache and method thereof 有权
标题翻译：具有描述符缓存的网络交换机及其方法
公开(公告)号：US06738838B2
公开(公告)日：2004-05-18
申请号：US10456767
申请日：2003-06-06
申请人： David Shemla , Rami Rozensvaig
发明人： David Shemla , Rami Rozensvaig
IPC分类号： G06F1300
CPC分类号： H04L49/901 , H04L49/3036 , H04L49/90
摘要： A device for writing descriptors, the device including a local memory comprising a multiplicity of mini-queues, wherein each of the mini-queues temporarily stores a plurality of descriptors, wherein each of the descriptors is associated with one of the data packets. Additionally including an output memory comprising a multiplicity of output queues, wherein each of the output queues in output memory is associated with one of the queues in said local memory, and a burst writer which writes N descriptors simultaneously from the mini-queue in the local memory to its associated output queue in output memory.
摘要翻译：一种用于写入描述符的设备，所述设备包括包括多个小型队列的本地存储器，其中每个所述小型队列临时存储多个描述符，其中每个描述符与所述数据分组之一相关联。另外包括包括多个输出队列的输出存储器，其中输出存储器中的每个输出队列与所述本地存储器中的一个队列相关联，以及突发写入器，其从本地的小型队列同时写入N个描述符内存到输出内存中的相关输出队列。

35. 发明授权

US5999981A Switching ethernet controller providing packet routing 失效
标题翻译：切换以太网控制器提供数据包路由
公开(公告)号：US5999981A
公开(公告)日：1999-12-07
申请号：US790149
申请日：1997-01-28
申请人： Avigdor Willenz , David Shemla , Yosi Sholt
发明人： Avigdor Willenz , David Shemla , Yosi Sholt
IPC分类号： H04L12/18 , H04L12/931 , H04L12/937 , H04L12/947 , H04L12/28
CPC分类号： H04L49/25 , H04L49/201 , H04L49/254 , H04L49/351
摘要： A switched Ethernet controller (SEC) device and associated method that provides processor based intervention in the packet routing decision process is provided. The method of routing a multicast packet between a source port on a source device and a plurality of destination ports on a plurality of destination devices, utilizes a processor. The method includes the steps of the source device receiving the multicast packet via the source port, the source device sending the multicast packet to the processor, the processor examining the multicast packet, the processor determining the plurality of destination devices and corresponding the plurality of destination ports based on the results obtained during the step of examining, the processor transferring the multicast packet to the plurality of destination devices, and the plurality of destination devices sending the multicast packet to the plurality of destination ports.
摘要翻译：提供了一种在分组路由决策过程中提供基于处理器的干预的交换以太网控制器（SEC）设备和相关联的方法。在源设备上的源端口与多个目的地设备上的多个目的地端口之间路由组播分组的方法利用处理器。该方法包括以下步骤：源设备经由源端口接收组播报文，源设备向处理器发送组播报文，处理器检查组播报文，处理器确定多个目标设备，并对应多个目的地基于在检查步骤中获得的结果，处理器将多播分组传送到多个目的地设备，以及将多播分组发送到多个目的地端口的多个目的地设备。

36. 发明授权

US5923660A Switching ethernet controller 失效
公开(公告)号：US5923660A
公开(公告)日：1999-07-13
申请号：US790155
申请日：1997-01-28
申请人： David Shemla , Avigdor Willenz
发明人： David Shemla , Avigdor Willenz
IPC分类号： H04L12/28 , H04L12/931 , H04L12/935 , H04L12/937 , H04L12/56
CPC分类号： H04L49/254 , H04L49/201 , H04L49/3009 , H04L49/3018 , H04L49/351
摘要： An Ethernet controller, for use within an Ethernet network of other Ethernet controller connected together by a bus, is provided. The Ethernet controller includes a plurality of ports including at least one bus port associated with ports connected to other switching Ethernet controllers, a hash table for storing addresses of ports within the Ethernet network, a hash table address control, a storage buffer including a multiplicity of contiguous buffers in which to temporarily store said packet, an empty list including a multiplicity of single bit buffers, a packet storage manager, a packet transfer manager and a write-only bus communication unit. The hash table address control hashes the address of a packet to initial hash table location values, changes the hash table location values by a fixed jump amount if the address values stored in the initial hash table location do not match the received address, and provides at least an output port number of the port associated with the received address. The packet storage manager associates the state of the bit of a single bit buffer with the empty or full state of an associated contiguous buffer and generates the address of a contiguous buffer. The packet transfer manager directs the temporarily stored packet to the port determined by said hash table control unit. The write-only bus communication unit is activated by the packet transfer manager, for transferring the packet out of the bus port by utilizing the bus for write only operations.

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