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31. 发明授权

US4980585A Method and apparatus for synthesizing digital waveforms 失效
标题翻译：用于合成数字波形的方法和装置
公开(公告)号：US4980585A
公开(公告)日：1990-12-25
申请号：US444670
申请日：1989-12-01
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03K5/00 , G06F1/025 , H03K5/156 , H03L7/099 , H04M1/50
CPC分类号： G06F1/025 , H04M1/505
摘要： An integrated circuit apparatus for performing digital synthesis of regular waveforms having transitions at arbitrary points in time is disclosed. A reference clock signal is provided as input to a synchronous delay line apparatus, producing a plurality of taps. The taps signal provides N inputs to a digital-to-time domain converter (DTC), where N is the resolution of the synthesized waveform, said DTC apparatus further receiving inputs from a pattern generator apparatus over a shifter apparatus and a pattern register apparatus. The DTC apparatus combines the taps signal and the input from said pattern register to produce a synthesized waveform. In the presently preferred embodiment, the DTC apparatus comprises a plurality of pairs of N-type and P-type devices connected as transmission gates. When the transmission gate is turned on, it transfers the input pattern bits to the output line. When the transmission gate is turned off, it effectively has an infinite impedance and isolates the input pattern from the output line. Only one transmission gate in the DTC apparatus is turned on at one time. The waveform pattern register apparatus has varying depths of master and slave latches. It receives pattern inputs from the pattern generator apparatus and outputs in three separate fields to the DTC apparatus. The bits of the first field of the pattern waveform register are implemented as a solitary master stage. The bits of the second field of the waveform pattern register are implemented as complete master-slave pairs. The bits of the third field of the waveform pattern register are implemented as master-slave-master triads.
摘要翻译：公开了一种用于在任意时间点进行具有过渡的规则波形的数字合成的集成电路装置。参考时钟信号作为输入提供给同步延迟线装置，产生多个抽头。抽头信号向数字 - 时域变换器（DTC）提供N个输入，其中N是合成波形的分辨率，所述DTC装置还通过移位器装置和模式寄存器装置从模式发生器装置接收输入。 DTC装置组合了抽头信号和来自所述模式寄存器的输入以产生合成波形。在目前优选的实施例中，DTC装置包括多个连接为传输门的N型和P型器件对。当传输门打开时，它将输入模式位传送到输出线。当传输门关闭时，它有效地具有无限阻抗，并将输入模式与输出线隔离。 DTC设备中只有一个传输门一次打开。波形图案寄存器装置具有不同深度的主锁存器和从锁存器。它从图案发生器装置接收图案输入，并在三个单独的场中输出到DTC装置。模式波形寄存器的第一个字段的位被实现为单独的主级。波形图案寄存器的第二个字段的位被实现为完整的主 - 从对。波形模式寄存器的第三个字段的位被实现为主从主器件三元组。

32. 发明授权

US4958133A CMOS complementary self-biased differential amplifier with rail-to-rail common-mode input-voltage range 失效
标题翻译： CMOS互补自偏置差分放大器，具有轨到轨共模输入电压范围
公开(公告)号：US4958133A
公开(公告)日：1990-09-18
申请号：US434339
申请日：1989-11-13
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03F3/45
CPC分类号： H03F3/45219 , H03F3/4565 , H03F3/45654 , H03F2203/45292 , H03F2203/45454
摘要： A CMOS complementary, self-biased, differential amplifier provides for a rail-to-rail common-mode input-voltage range of operation. A self-biasing scheme is used to provide negative feedback to the amplifier in order to assist in providing a common-mode rejection but providing high gain amplification for differential-mode amplification.
摘要翻译： CMOS互补的自偏置差分放大器提供轨到轨共模输入电压范围的操作。自偏置方案用于向放大器提供负反馈，以帮助提供共模抑制，但为差模放大提供高增益放大。

33. 发明授权

US4499428A IC Delay conversion operational amplifier 失效
标题翻译： IC延迟转换运算放大器
公开(公告)号：US4499428A
公开(公告)日：1985-02-12
申请号：US529212
申请日：1983-09-06
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03F3/393 , H03F3/38 , H03F3/16
CPC分类号： H03F3/393
摘要： An operational amplifier suitable for MOS fabrication is described. The amplifier operates adequately over a large range of process, temperature and voltage supply variations. Two identical delay lines are employed in the amplifier. One controls the frequency of oscillation of an oscillator. The oscillator's output is used to control a sample-and-hold circuit, is delayed through the second delay circuit, and is used through a gate circuit to provide a sampled potential for the sample-and-hold circuit.
摘要翻译：描述适用于MOS制造的运算放大器。放大器在大范围的工艺，温度和电压供应变化范围内充分运行。在放大器中采用两条相同的延迟线。一个控制振荡器的振荡频率。振荡器的输出用于控制采样保持电路，通过第二延迟电路延迟，并通过门电路使用来为采样保持电路提供采样电位。

34. 发明授权

US07843247B1 Method and apparatus for controlled voltage level shifting 有权
标题翻译：用于控制电压电平转换的方法和装置
公开(公告)号：US07843247B1
公开(公告)日：2010-11-30
申请号：US12506024
申请日：2009-07-20
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03L5/00
CPC分类号： H03F3/45475 , H03F2203/45101 , H03F2203/45136
摘要： The disclosed technology provides a method of and an apparatus for voltage level shifting. A voltage level shifter includes two level shifting circuits and a differential amplifier. The differential amplifier forms a feedback loop with one level shifting circuit. The feedback loop controls the level shifting operation of both level shifting circuits. The differential amplifier can operate to provide a control signal that causes a level-shifted signal in the feedback loop to match a target signal. The two level shifting circuits can perform their level shifting operation based on the control signal.
摘要翻译：所公开的技术提供了用于电压电平转换的方法和装置。电压电平移位器包括两个电平移位电路和一个差分放大器。差分放大器与一个电平移位电路形成反馈回路。反馈回路控制两个电平移位电路的电平移位操作。差分放大器可以操作以提供使反馈环路中的电平移位信号与目标信号匹配的控制信号。两个电平移位电路可以基于控制信号执行电平移位操作。

35. 发明申请

US20080018367A1 Method and Apparatus for Generating Frequency Divided Signals 有权
标题翻译：用于产生分频信号的方法和装置
公开(公告)号：US20080018367A1
公开(公告)日：2008-01-24
申请号：US11740638
申请日：2007-04-26
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03B19/00
CPC分类号： H03K5/1534 , H03K23/50
摘要： In a method for dividing a frequency of a clock signal, a first frequency divided signal is generated based on a clock signal. Rising edges in the first frequency divided signal are detected. Alternatively, falling edges in the first frequency divided signal are detected. An edge detection signal that includes a pulse for each detected edge is generated. A second frequency divided signal is generated based on the edge detection signal.
摘要翻译：在分频时钟信号的频率的方法中，基于时钟信号产生第一分频信号。检测第一分频信号中的上升沿。或者，检测第一分频信号中的下降沿。生成包含每个检测边缘的脉冲的边缘检测信号。基于边缘检测信号产生第二分频信号。

36. 发明授权

US07236518B2 Deskewing differential repeater 失效
标题翻译：偏移差分中继器
公开(公告)号：US07236518B2
公开(公告)日：2007-06-26
申请号：US10280873
申请日：2002-10-24
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H04L25/52
CPC分类号： H03K5/1515 , G06F1/10 , H03K3/356113 , H04L25/0272 , H04L25/242
摘要： A device including an input to receive a differential waveform pair from a transmission line, the differential waveform pair including a first waveform and a second waveform. The device also includes a repeater to generate a refreshed first output waveform and a refreshed second output waveform. The refreshed first output waveform is substantially similar to an inverted copy of the first waveform and is generated after a signal transition of the first waveform and after a complementary signal transition of the second waveform. The refreshed second output waveform is substantially similar to an inverted copy of the second waveform and is generated substantially simultaneously with generation of the first output waveform.
摘要翻译：一种包括用于从传输线接收差分波形对的输入的装置，所述差分波形对包括第一波形和第二波形。该装置还包括一个中继器，用于产生刷新的第一输出波形和刷新的第二输出波形。刷新的第一输出波形基本上类似于第一波形的反转副本，并且在第一波形的信号转换和第二波形的互补信号转换之后产生。刷新的第二输出波形基本上类似于第二波形的反相，并且与第一输出波形的产生基本同时地产生。

37. 发明授权

US06856172B1 Sequential logic circuit for frequency division 失效
公开(公告)号：US06856172B1
公开(公告)日：2005-02-15
申请号：US10678898
申请日：2003-10-02
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03K23/54 , H03K19/00
CPC分类号： H03K23/54
摘要： A circuit to divide down the frequency of a clock signal, where embodiment circuits comprise a set-reset flip-flop feeding its output to a shift register, and combinational logic to provide feedback from the shift register to the set input port, reset input port, or both set and reset input ports of the set-reset flip-flop. The set-reset flip-flop and shift register are clocked by the clock signal. The output signal of the circuit may be taken at any output port of the shift register or the set-reset flip-flop. In one embodiment, the state of the shift register is represented by the set of Boolean values Q , i=1, 2, . . . , N−1, and the combinational logic provides to the set input port of the set-reset flip-flop the Boolean value {Q# . . . Q# }, where Q# is the Boolean complement of Q , Q# is provided by the set-reset flip-flop, is Boolean AND, and M is a positive integer not greater than N; and the combinational logic also provides the Boolean value {Q . . . Q } to the reset input port of the set-reset flip-flop, where L is a positive integer not greater than N. For such an embodiment, the frequency of the output signal is that of the clock signal divided down by the divisor D where D L+M, and the duty cycle of the output signal is L/D.

38. 发明授权

US06633186B1 Speed-locked loop to provide speed information based on die operating conditions 失效
标题翻译：速度锁定环路，以提供基于工作条件的速度信息
公开(公告)号：US06633186B1
公开(公告)日：2003-10-14
申请号：US09550452
申请日：2000-04-17
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03L706
CPC分类号： H03L7/0805 , H03L7/0995
摘要： A speed-locked loop (SLL) circuit to automatically determine overall chip speed, which is a function of the combination of supply voltage, temperature, and processing parameters, and to output the speed information in digital form to speed-compensating circuits in order to significantly reduce their sensitivity to operating conditions. Through negative feedback, a digitally controlled ring oscillator (DCO) is forced to lock at an oscillation frequency close to that specified by a six-bit speed constant input. A three-bit control bus varies the DCO oscillation frequency under digital control until the SLL achieves lock. When the SLL has achieved lock it latches the DCO control bus and outputs it as the speed information. The speed constant input may be varied under software control in order to determine the speed constant value that optimizes performance of speed-compensating circuits under SLL control.
摘要翻译：一种快速锁定回路（SLL）电路，用于自动确定整体芯片速度，这是电源电压，温度和处理参数的组合的函数，并以数字形式将速度信息输出到速度补偿电路，以便显着降低其对操作条件的敏感性。通过负反馈，数字控制环形振荡器（DCO）被迫以接近6位速度常数输入指定的振荡频率进行锁定。三位控制总线在数字控制下改变DCO振荡频率，直到SLL达到锁定。当SLL达到锁定时，锁存DCO控制总线并将其作为速度信息输出。速度常数输入可以在软件控制下进行变化，以确定在SLL控制下优化速度补偿电路性能的速度常数值。

39. 发明授权

US06469579B2 Boosted high gain, very wide common mode range, self-biased operational amplifier 有权
标题翻译：增益高，共模范围非常宽，自偏置运算放大器
公开(公告)号：US06469579B2
公开(公告)日：2002-10-22
申请号：US09547780
申请日：2000-04-12
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03F345
CPC分类号： H03F3/45677 , H03F3/45192
摘要： A boosted high gain, very wide common mode range, self-biased operational amplifier comprising complementary differential transistor pairs biased by biasing transistors and current mirrors, and comprising two amplifiers, each connected to bias an output cascode transistor so as to provide a very high amplifier output impedance, wherein the biasing transistors and current mirrors are all self-biased via negative feedback.
摘要翻译：提高的高增益，非常宽的共模范围，自偏置运算放大器包括通过偏置晶体管和电流镜偏置的互补差分晶体管对，并且包括两个放大器，每个放大器连接到偏置输出共源共栅晶体管，以便提供非常高的放大器输出阻抗，其中偏置晶体管和电流镜都通过负反馈自偏置。

40. 发明授权

US5546431A Programmable digital filter with substantially equal bandwidth increments 失效
标题翻译：可编程数字滤波器，带宽增量基本相等
公开(公告)号：US5546431A
公开(公告)日：1996-08-13
申请号：US225902
申请日：1994-04-11
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03H17/02 , H04B1/10 , G06F17/17
CPC分类号： H03H17/0294
摘要： A shifter circuit of a digital filter circuit for providing an adjustable correction coefficient (.beta.) for the digital filter is described. The shifter circuit includes a first shifter for providing a first shift amount (S.sub.1) to an input signal, and a second shifter for providing a second shift amount (S.sub.2) to the input signal. Logic circuitry is provided in the shifter circuit that is coupled to the first and second shifters for receiving outputs of the first and second shifters under control of a control signal to generate an output signal of the shifter circuit with the adjustable correction coefficient (.beta.) such that digital filter has an adjustable bandwidth (BW) that is adjusted at a fine and substantially equal bandwidth increment. The adjustable correction coefficient (.beta.)is selectively derived from a combination of 2.sup.-S1 and 2.sup.-S2 such that the adjustable bandwidth (BW) is obtained from the equation: BW=-In(1-.beta.)/2.pi.T.sub.P.
摘要翻译：描述了用于为数字滤波器提供可调校正系数（β）的数字滤波器电路的移位电路。移位器电路包括用于向输入信号提供第一移位量（S1）的第一移位器和用于向输入信号提供第二移位量（S2）的第二移位器。在移位器电路中提供逻辑电路，其耦合到第一和第二移位器，用于在控制信号的控制下接收第一和第二移位器的输出，以产生具有可调校正系数（β）的移位器电路的输出信号，该数字滤波器具有可调节带宽（BW），其被调整为精细且基本相等的带宽增量。选择性地从2-S1和2-S2的组合导出可调节校正系数（β），使得可调节带宽（BW）从以下等式获得：BW = -In（1-β）/2πTP。

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