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1. 发明授权

US07839220B2 Phase-locked loop runaway detector 有权
标题翻译：锁相环失控检测器
公开(公告)号：US07839220B2
公开(公告)日：2010-11-23
申请号：US11743604
申请日：2007-05-02
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/02 , H03L7/0891 , H03L7/095
摘要： In a circuit having a runaway detector coupled to a phase-locked loop (PLL), the PLL may include a loop filter to receive a control voltage within the PLL and provide a filtered control voltage and a voltage-controlled oscillator to receive the filtered control voltage and provide an output clock signal. The runaway detector may provide a control signal for adjusting the filtered control voltage in response to a predetermined PLL condition. The runaway detector may include a comparator to receive a first and second input voltages, where the second input voltage is based on the output clock signal. When the predetermined PLL condition exists, the runaway detector may be active to adjust the filtered control voltage, thereby enabling the PLL to return to a lock condition.
摘要翻译：在具有耦合到锁相环（PLL）的失控检测器的电路中，PLL可以包括环路滤波器，以在PLL内接收控制电压并提供经滤波的控制电压和压控振荡器以接收经滤波的控制电压并提供输出时钟信号。失控检测器可以提供用于响应于预定的PLL条件来调整经滤波的控制电压的控制信号。失控检测器可以包括用于接收第一和第二输入电压的比较器，其中第二输入电压基于输出时钟信号。当存在预定的PLL条件时，失控检测器可以被激活以调整滤波的控制电压，从而使得PLL能够返回到锁定状态。

2. 发明授权

US07800417B2 Method and apparatus for generating frequency divided signals 有权
标题翻译：用于产生分频信号的方法和装置
公开(公告)号：US07800417B2
公开(公告)日：2010-09-21
申请号：US11740638
申请日：2007-04-26
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03B19/00
CPC分类号： H03K5/1534 , H03K23/50
摘要： In a method for dividing a frequency of a clock signal, a first frequency divided signal is generated based on a clock signal. Rising edges in the first frequency divided signal are detected. Alternatively, falling edges in the first frequency divided signal are detected. An edge detection signal that includes a pulse for each detected edge is generated. A second frequency divided signal is generated based on the edge detection signal.
摘要翻译：在分频时钟信号的频率的方法中，基于时钟信号产生第一分频信号。检测第一分频信号中的上升沿。或者，检测第一分频信号中的下降沿。生成包含每个检测边缘的脉冲的边缘检测信号。基于边缘检测信号产生第二分频信号。

3. 发明申请

US20080246525A1 LEVEL-RESTORED FOR SUPPLY-REGULATED PLL 有权
标题翻译：用于供应调节PLL的电平恢复器
公开(公告)号：US20080246525A1
公开(公告)日：2008-10-09
申请号：US12061373
申请日：2008-04-02
申请人： Mel BAZES
发明人： Mel BAZES
IPC分类号： H03K5/02
CPC分类号： H03K5/003 , H03K3/356113 , H03K5/02
摘要： The present disclosure provides for a processor that can include digital processing circuitry that receives a digital clock signal from a supply regulated phase locked loop. The supply regulated phase locked loop can include a voltage controlled oscillator that can output an analog signal and a level restorer that can receive the analog signal from the voltage controlled oscillator and can translate the analog output into a digital signal that corresponds to an analog output of the voltage controlled oscillator. The supply regulated phase locked loop can receive an analog input having an input voltage that is within a range of acceptable input voltages. The supply regulated phase locked loop can also be configured to generate the digital output signal, such that the range of acceptable input voltages includes voltage values that are greater than and less than the output voltage.
摘要翻译：本公开提供了一种处理器，其可以包括从供应调节锁相环接收数字时钟信号的数字处理电路。电源调节锁相环可以包括可以输出模拟信号的压控振荡器和能够从压控振荡器接收模拟信号的电平恢复器，并且可以将模拟输出转换成对应于模拟输出的模拟输出的数字信号压控振荡器。电源调节锁相环可以接收具有在可接受的输入电压范围内的输入电压的模拟输入。电源调节锁相环也可以被配置为产生数字输出信号，使得可接受的输入电压的范围包括大于和小于输出电压的电压值。

4. 发明申请

US20060290334A1 Duty cycle mode switching voltage regulator 审中-公开
标题翻译：占空比模式开关稳压器
公开(公告)号：US20060290334A1
公开(公告)日：2006-12-28
申请号：US11168114
申请日：2005-06-28
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： G05F1/00
CPC分类号： H02M3/156 , H02M3/1563
摘要： One disclosed method includes controlling an output voltage to track a reference voltage by using a feedback loop to monitor an output duty cycle and to maintain an output voltage that is substantially constant relative to the reference voltage.
摘要翻译：一种公开的方法包括通过使用反馈回路来控制输出电压来跟踪参考电压以监测输出占空比并且维持相对于参考电压基本上恒定的输出电压。

5. 发明授权

US06982580B2 Speed-locked loop to provide speed information based on die operating conditions 失效
公开(公告)号：US06982580B2
公开(公告)日：2006-01-03
申请号：US10456030
申请日：2003-06-06
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03L7/0995
摘要： A speed-locked loop (SLL) circuit to automatically determine overall chip speed, which is a function of the combination of supply voltage, temperature, and processing parameters, and to output the speed information in digital form to speed-compensating circuits in order to significantly reduce their sensitivity to operating conditions. Through negative feedback, a digitally controlled ring oscillator (DCO) is forced to lock at an oscillation frequency close to that specified by a six-bit speed constant input. A three-bit control bus varies the DCO oscillation frequency under digital control until the SLL achieves lock. When the SLL has achieved lock it latches the DCO control bus and outputs it as the speed information. The speed constant input may be varied under software control in order to determine the speed constant value that optimizes performance of speed-compensating circuits under SLL control.

6. 发明授权

US5991339A Adaptive equalization using a minimum- jitter criterion 失效
标题翻译：使用最小抖动标准进行自适应均衡
公开(公告)号：US5991339A
公开(公告)日：1999-11-23
申请号：US8050
申请日：1998-01-16
申请人： Mel Bazes , Rafi Ben-Tal
发明人： Mel Bazes , Rafi Ben-Tal
IPC分类号： H03H11/04 , H03H11/12 , H03H7/30
CPC分类号： H03H11/1291 , H03H11/04
摘要： An adaptive equalizer is implemented using digital feedback control and using jitter as the adjustment criteria. An adjustable transfer function is implemented to equalize an input signal to enhance the frequency response of the associated system. Jitter is determined for the filtered signal, and the frequency response of the transfer function is varied accordingly by applying a digital adjustment signal to the transfer function structure (for example, a lead-lag filter). The adaptive equalizer can thereby adapt to various transmission medium lengths and signal degradation levels.
摘要翻译：使用数字反馈控制和使用抖动作为调整标准来实现自适应均衡器。实现可调传递函数以均衡输入信号以增强相关系统的频率响应。针对滤波后的信号确定抖动，通过对传递函数结构（例如，超前滞后滤波器）应用数字调整信号来相应地改变传递函数的频率响应。因此，自适应均衡器可以适应各种传输介质长度和信号劣化水平。

7. 发明授权

US5880615A Method and apparatus for detecting differential threshold levels while compensating for baseline wander 失效
标题翻译：用于在补偿基线漂移的同时检测差分阈值水平的方法和装置
公开(公告)号：US5880615A
公开(公告)日：1999-03-09
申请号：US764720
申请日：1996-12-10
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03K5/08 , H03K5/1532 , H03L5/00
CPC分类号： H03K5/082 , H03K5/1532
摘要： A method and an apparatus for detecting differential threshold levels of a differential signal being carried in first and second lines while compensating for baseline wander. In one embodiment, first and second single-ended signals and a common mode signal are generated in response to the first and second lines. First and second peak signals are then generated in response to the first and second single-ended signals and the common mode signal. Finally, first and second threshold signals are generated which are compared with the first and second single-ended signals to generate first and second output signals indicating first and second differential threshold levels.
摘要翻译：一种用于在补偿基线漂移的同时检测在第一和第二行中携带的差分信号的差分阈值电平的方法和装置。在一个实施例中，响应于第一和第二行产生第一和第二单端信号和共模信号。然后响应于第一和第二单端信号和共模信号产生第一和第二峰值信号。最后，产生与第一和第二单端信号进行比较的第一和第二阈值信号，以产生指示第一和第二差分阈值电平的第一和第二输出信号。

8. 发明授权

US5644262A Digitally controlled capacitive load 失效
标题翻译：数字控制电容负载
公开(公告)号：US5644262A
公开(公告)日：1997-07-01
申请号：US621732
申请日：1996-03-21
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03K5/13 , H03K17/28
CPC分类号： H03K5/131
摘要： An integrated circuit for selectively providing delay to a waveform carried on a signal line. With the present invention, a waveform is carried by a signal line to which a digitally-controlled capacitive load is coupled. A digital enable line is directly coupled to the capacitive load which either activates or deactivates the capacitive load. When the enable line is in the active state, the capacitive load is activated and the load therefore has maximum capacitance. Accordingly, the delay of the waveform carried on the signal line is also maximized. When the enable line is in the inactive state, the capacitive load has minimal capacitance and the delay of the signal being carried on the signal line is therefore minimized.
摘要翻译：一种集成电路，用于选择性地向信号线上携带的波形提供延迟。利用本发明，波形由数字控制的容性负载耦合到的信号线承载。数字使能线直接耦合到电容性负载，其可以激活或去激活电容性负载。当使能线处于活动状态时，容性负载被激活，因此负载具有最大电容。因此，信号线上携带的波形的延迟也最大化。当使能线处于非活动状态时，容性负载具有最小的电容，因此在信号线上承载的信号的延迟最小化。

9. 发明授权

US4937476A Self-biased, high-gain differential amplifier with feedback 失效
标题翻译：具有反馈功能的自偏置高增益差分放大器
公开(公告)号：US4937476A
公开(公告)日：1990-06-26
申请号：US462879
申请日：1990-01-02
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03H19/00 , H03K5/24 , H03K17/30 , H03K17/687
CPC分类号： H03H19/004 , H03K17/302 , H03K17/6872 , H03K5/2472
摘要： A self-biased, high-gain differential amplifier which is substantially immune to process and temperature variations. A first pair of CMOS transistors is coupled to operate in an active region and an output from the common junction is coupled to drive a second pair of CMOS transistors. The second pair of CMOS transistors have their outputs coupled to provide a negative feedback to the first pair of CMOS transistors. A third pair of CMOS transistors is coupled in parallel to the first pair of CMOS transistors for accepting an input signal and generating an output, wherein the output is a function of the input signal in relation to a reference voltage. A fourth pair of CMOS transistors is coupled to be driven by the third pair of CMOS transistors and provides a CMOS compatible signal which switches between two CMOS logic states.
摘要翻译：自偏置高增益差分放大器，其基本上不受过程和温度变化的影响。第一对CMOS晶体管被耦合以在有源区域中工作，并且来自公共结的输出被耦合以驱动第二对CMOS晶体管。第二对CMOS晶体管的输出被耦合以向第一对CMOS晶体管提供负反馈。第三对CMOS晶体管与第一对CMOS晶体管并联耦合以接受输入信号并产生输出，其中输出是与参考电压相关的输入信号的函数。第四对CMOS晶体管被耦合以由第三对CMOS晶体管驱动，并提供在两个CMOS逻辑状态之间切换的CMOS兼容信号。

10. 发明授权

US4849661A CMOS input buffer with switched capacitor reference voltage generator 失效
标题翻译：具有开关电容参考电压发生器的CMOS输入缓冲器
公开(公告)号：US4849661A
公开(公告)日：1989-07-18
申请号：US207670
申请日：1988-06-16
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03H19/00 , H03K5/24
CPC分类号： H03H19/004 , H03K5/2481
摘要： An input buffer circuit for providing corresponding CMOS compatible signals to an input signal. The input buffer circuit is comprised of a switched-capacitor voltage division network for providing a reference voltage to a comparator. The comparator accepts an input voltage and determines if the input voltage is greater or less than the reference voltage and generates a CMOS compatible output, which is determined by the value of the input signal in reference to the reference voltage. The reference voltage generator is comprised of two capacitive devices, wherein the first capacitive device is charged and the second capacitive device is discharged during a first time period and the charges on the two capacitive devices are shared during a second time period. A ratio of the capacitances of these two capacitive devices determines the voltage value at the junction of the two capacitors, which then determines the reference voltage. The two capacitors are comprised of an n-type device and a p-type device to provide immunity to variations in process and temperature.
摘要翻译：一种用于向输入信号提供相应的CMOS兼容信号的输入缓冲电路。输入缓冲电路包括用于向比较器提供参考电压的开关电容器分压网络。比较器接受输入电压并确定输入电压是否大于或小于参考电压，并产生CMOS兼容输出，该输出由参考电压的输入信号的值确定。参考电压发生器由两个电容性装置组成，其中第一电容性装置被充电，并且第二电容性装置在第一时间段期间被放电，并且两个电容性装置上的电荷在第二时间段期间被共享。这两个电容器件的电容比决定了两个电容器的结的电压值，然后确定参考电压。两个电容器由n型器件和p型器件组成，以提供对工艺和温度变化的抗扰性。

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