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31. 发明申请

US20150249143A1 Method For Forming Oxide Below Control Gate In Vertical Channel Thin Film Transistor 有权
标题翻译：在垂直通道薄膜晶体管中形成氧化物低于控制栅的方法
公开(公告)号：US20150249143A1
公开(公告)日：2015-09-03
申请号：US14193451
申请日：2014-02-28
申请人： SanDisk 3D LLC
发明人： Michiaki Sano , Kensuke Yamaguchi , Akira Nakada , Naohito Yanagida
IPC分类号： H01L29/66 , H01L29/04 , H01L21/28 , H01L29/78 , H01L21/306
CPC分类号： H01L29/66666 , H01L21/28238 , H01L27/11556 , H01L27/11582 , H01L29/04 , H01L29/7827
摘要： A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line.
摘要翻译：垂直沟道晶体管的制造工艺提供所需的控制栅 - 漏重叠以及控制栅极与下面的金属线之间的充分隔离。晶体管的主体形成在诸如柱状的金属线上。金属线被氧化形成具有膨胀体积的金属氧化物区域。然后沉积栅极绝缘体材料和控制栅极材料。蚀刻所得到的结构以形成用于每个晶体管的单独的控制栅极，并暴露金属氧化物。执行另外的蚀刻以去除金属氧化物，在控制栅极下和周围形成空隙。绝缘填充空隙。示例性实施例是垂直位线存储器件，其中晶体管将垂直位线连接到水平位线。

32. 发明授权

US09123392B1 Non-volatile 3D memory with cell-selectable word line decoding 有权
标题翻译：具有单元格可选字线解码的非易失性3D存储器
公开(公告)号：US09123392B1
公开(公告)日：2015-09-01
申请号：US14229482
申请日：2014-03-28
申请人： SanDisk 3D LLC
发明人： Tianhong Yan , Roy Edwin Scheuerlein
IPC分类号： G11C11/00 , G11C5/02 , G11C13/00
CPC分类号： G11C13/0021 , G11C5/025 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/249
摘要： A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements are each accessible by a word line in a plane and a local bit line. The three-dimensional array includes a two-dimensional array of pillar lines through the multiple layers of planes. The pillar lines are of a first type that act as local bit lines and a second type that provide access to the word lines by having respective memory elements preset to a permanently low resistance state for connecting second-type pillar lines for exclusive access to respective word lines. An array of metal lines on the substrate is switchably connected to the vertical bit lines to provide access to the local bit lines and the word lines.
摘要翻译：存储元件的三维阵列形成在位于半导体衬底上方不同距离的多个平面层上。存储器元件可以通过平面中的字线和局部位线来访问。三维阵列包括通过多层平面的两列立柱阵列。柱线是作为局部位线的第一类型和第二类型，其通过将相应的存储器元件预设为永久低电阻状态来提供对字线的访问，用于连接用于独占访问的相应字的第二类型支柱线条。衬底上的金属线阵列可切换地连接到垂直位线以提供对局部位线和字线的访问。

33. 发明授权

US09054308B1 Plasma reduction method for modifying metal oxide stoichiometry in ReRAM 有权
标题翻译：用于修改ReRAM中金属氧化物化学计量的等离子体还原法
公开(公告)号：US09054308B1
公开(公告)日：2015-06-09
申请号：US14196647
申请日：2014-03-04
申请人： SanDisk 3D LLC
发明人： Tong Zhang , Timothy James Minvielle , Chu-Chen Fu , Wipul Jayasekara
IPC分类号： H01L21/00 , H01L21/16 , H01L47/00 , H01L45/00
CPC分类号： H01L45/1641 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1616
摘要： A fabrication process for a resistance-switching memory cell uses metal oxide as a resistance-switching material. A metal oxide film having an initial stoichiometry is deposited on an electrode using atomic layer deposition. A changed stoichiometry is provided for a portion of the metal oxide film using a plasma reduction process, separate from the atomic layer deposition, and another electrode is formed adjacent to the changed stoichiometry portion. The film deposition and the plasma reduction can be performed in separate chambers where conditions such as temperature are optimized. The metal oxide film may be deposited on a vertical sidewall in a vertical bit line 3d memory device. Optionally, the mean free path of hydrogen ions during the plasma reduction process is adjusted to increase the uniformity of the vertical metal oxide film. The adjustment can involve factors such as RF power, pressure and a bias of the wafer.
摘要翻译：电阻切换存储单元的制造工艺使用金属氧化物作为电阻切换材料。使用原子层沉积将具有初始化学计量的金属氧化物膜沉积在电极上。使用与原子层沉积分离的等离子体还原法，对于金属氧化物膜的一部分提供了改变的化学计量，并且与改变的化学计量部分相邻地形成另一电极。膜沉积和等离子体还原可以在诸如温度等条件优化的分离室中进行。金属氧化物膜可以沉积在垂直位线3d存储器件中的垂直侧壁上。可选地，调整等离子体还原过程期间氢离子的平均自由程，以增加垂直金属氧化物膜的均匀性。该调整可以涉及诸如RF功率，压力和晶片偏置的因素。

34. 发明授权

US09054307B2 Resistive random access memory cells having metal alloy current limiting layers 有权
标题翻译：具有金属合金限流层的电阻随机存取存储单元
公开(公告)号：US09054307B2
公开(公告)日：2015-06-09
申请号：US14317155
申请日：2014-06-27
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim , Tim Minvielle , Dipankar Pramanik , Takeshi Yamaguchi
IPC分类号： G11C13/00 , G11C7/00 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1608 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C2213/56 , G11C2213/76 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/16
摘要： Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.
摘要翻译：提供了诸如电阻随机存取存储器（ReRAM）单元的半导体器件，其包括由过渡金属的合金形成的限流层。这种合金的一些实例包括还可以包括镍，铝和/或硅的含铬合金。其它实例包括也可以包括硅和碳的组合或铝和氮的组合的含钽和/或钛的合金。这些限流层可具有至少约1欧姆 - 厘米的电阻率。即使当这些层受到强电场和/或高温处理时，也保持该电阻率水平。在一些实施例中，限流层的击穿电压为至少约8V。层的高电阻率允许在保持其性能的同时缩小包括这些层的半导体器件的尺寸。

35. 发明授权

US09047943B2 Non-volatile storage system biasing conditions for standby and first read 有权
标题翻译：非易失性存储系统偏置条件用于待机和首次读取
公开(公告)号：US09047943B2
公开(公告)日：2015-06-02
申请号：US14197136
申请日：2014-03-04
申请人： SANDISK 3D LLC
发明人： Chang Siau
IPC分类号： G11C16/10 , G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： G11C13/004 , G11C13/0026 , G11C16/10 , G11C2013/005 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/149
摘要： Methods for reducing power consumption of a non-volatile storage system and reducing first read latency are described. The non-volatile storage system may include a cross-point memory array. In some embodiments, during a standby mode, the memory array may be biased such that both word lines and bit lines are set to ground. During transition of the memory array from the standby mode to a read mode, a selected word line comb may be set to a read voltage while the unselected word lines and the bit lines remain at ground. During the read mode, memory cells connected to the selected bit lines and the selected word line comb may be sensed while the selected bit lines are biased to a selected bit line voltage equal to or close to ground and the unselected bit lines are left floating after initially being set to ground.
摘要翻译：描述了用于降低非易失性存储系统的功耗并减少第一读延迟的方法。非易失性存储系统可以包括交叉点存储器阵列。在一些实施例中，在待机模式期间，存储器阵列可被偏置，使得字线和位线都被设置为接地。在存储器阵列从待机模式转换到读取模式期间，所选择的字线梳可以被设置为读取电压，而未选择的字线和位线保持在地。在读取模式期间，可以感测连接到所选位线和所选择的字线梳的存储单元，同时所选择的位线被偏置到等于或接近地的选定位线电压，并且未选择的位线在最初被置于地面。

36. 发明授权

US09034689B2 Non-volatile storage with metal oxide switching element and methods for fabricating the same 有权
标题翻译：具有金属氧化物开关元件的非易失性存储器及其制造方法
公开(公告)号：US09034689B2
公开(公告)日：2015-05-19
申请号：US13848603
申请日：2013-03-21
申请人： SanDisk 3D LLC
发明人： Deepak C. Sekar , Franz Kreupl , Peter Rabkin , Chu-Chen Fu
IPC分类号： H01L21/00 , H01L45/00 , G11C13/00 , H01L27/102 , H01L27/24
CPC分类号： H01L45/146 , G11C13/0007 , G11C2213/35 , G11C2213/71 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/1641 , H01L45/1675
摘要： Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element. The titanium might be implanted into the metal oxide while depositing the metal oxide, or after deposition of the metal oxide.
摘要翻译：本文公开了具有可逆电阻率开关元件的非易失性存储元件及其制造技术。可逆电阻率开关元件可以通过在顶部电极上沉积防氧扩散材料（例如，重掺杂的Si，W，WN）来形成。可以将陷阱钝化材料（例如，氟，氮，氢，氘）并入到可逆电阻率切换元件的底部电极，金属氧化物区域或顶部电极中的一个或多个中。一个实施例包括在金属氧化物和顶部电极之间具有双层覆盖层的可逆电阻率开关元件。制造该器件可以包括沉积（未反应的）钛并原位沉积二氧化钛而没有空气破裂。一个实施例包括将钛结合到可逆电阻率开关元件的金属氧化物中。可以在沉积金属氧化物的同时或在沉积金属氧化物之后将钛注入金属氧化物中。

37. 发明申请

US20150123071A1 Method for Forming Metal Oxides and Silicides in a Memory Device 有权
标题翻译：在存储器件中形成金属氧化物和硅化物的方法
公开(公告)号：US20150123071A1
公开(公告)日：2015-05-07
申请号：US14598499
申请日：2015-01-16
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Dipankar Pramanik , Tony P. Chiang , Tim Minvielle , Takeshi Yamaguchi
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L27/101 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.
摘要翻译：本发明的实施例一般涉及用于制造这种存储器件的存储器件和方法。在一个实施例中，一种用于制造电阻式开关存储器件的方法包括在设置在衬底上的下电极上沉积金属层，并将该金属层暴露于活性氧源，同时将衬底加热至约300 约600℃，并且在氧化过程中从金属层的上部形成金属氧化物层。下部电极含有硅材料，金属层含有铪或锆。在氧化处理之后，该方法还包括将衬底加热至大于600℃至约850℃的范围内的退火温度，同时在硅化期间从金属层的下部形成金属硅化物层处理。

38. 发明授权

US09007810B2 ReRAM forming with reset and iload compensation 有权
标题翻译： ReRAM形成复位和iload补偿
公开(公告)号：US09007810B2
公开(公告)日：2015-04-14
申请号：US13781503
申请日：2013-02-28
申请人： SanDisk 3D LLC
发明人： Chang Siau
IPC分类号： G11C11/00 , G11C13/00 , G11C7/20 , G11C29/02
CPC分类号： G11C13/0002 , G11C7/20 , G11C13/0064 , G11C13/0069 , G11C29/028 , G11C2013/0083 , G11C2013/0088
摘要： FORMING reversible resistivity-switching elements is described herein. The FORMING voltage may be halted if the current through the memory cell reaches some reference current. The reference current may depend on how many groups of memory cells have been FORMED. This can help to increase the accuracy of determining when to halt the FORMING voltage. After the FORMING voltage is applied, a RESET voltage may be applied to those memory cells that have a resistance that is lower than a reference resistance to raise the resistance of those memory cells. By raising the resistance, the leakage current of these memory cells when other groups are programmed may be less. This, in turn, helps to prevent FORMING of the other groups from slowing down. A reason why this helps to prevent the slowdown is that the FORMING voltage may be kept near a desired level.
摘要翻译：这里描述了形成可逆电阻率开关元件。如果通过存储单元的电流达到某个参考电流，则可能会停止FORMING电压。参考电流可能取决于已经形成了多少组存储器单元。这有助于提高确定何时停止FORMING电压的准确性。在施加FORMING电压之后，可以将RESET电压施加到具有低于参考电阻的电阻的那些存储单元，以提高那些存储单元的电阻。通过提高电阻，当其他组被编程时，这些存储器单元的漏电流可能较小。这反过来又有助于防止其他群体的形成减慢。为什么这有助于防止减速的原因是，FORMING电压可能保持在所需的水平附近。

39. 发明授权

US08995172B2 Nonvolatile memory device having a current limiting element 有权
标题翻译：具有限流元件的非易失性存储器件
公开(公告)号：US08995172B2
公开(公告)日：2015-03-31
申请号：US14186726
申请日：2014-02-21
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim
IPC分类号： G11C11/00 , H01L29/02 , H01L45/00 , G11C13/00 , H01L27/24
CPC分类号： H01L45/1253 , G11C13/0007 , G11C13/003 , G11C2213/56 , G11C2213/76 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/1616
摘要： Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.
摘要翻译：本发明的实施例通常包括一种形成非易失性存储器件的方法，该非易失性存储器件包含由于添加限定在其中的限流部件而具有改进的器件切换性能和寿命的电阻式开关存储元件。在一个实施例中，限流部件包括至少一层电阻材料，其被配置为提高所形成的电阻式开关存储元件的开关性能和寿命。所形成的限流层或电阻层的电性能被配置为在逻辑状态编程步骤（即“设定”和“复位”步骤）期间通过添加固定的串联电阻来降低通过可变电阻层的电流在形成在非易失性存储器件中的电阻式开关存储元件中。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。

40. 发明授权

US08987865B2 Memory device having an integrated two-terminal current limiting resistor 有权
标题翻译：存储器件具有集成的两端限流电阻
公开(公告)号：US08987865B2
公开(公告)日：2015-03-24
申请号：US14288003
申请日：2014-05-27
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Dipankar Pramanik , Tony P. Chiang , Mankoo Lee
IPC分类号： H01L29/8605 , H01L45/00 , H01L27/24
CPC分类号： H01L45/14 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092 , G11C2213/76 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
摘要翻译：提供了并入电阻式开关存储单元或装置中以形成具有改进的器件性能和寿命的存储器件的电阻器结构。电阻器结构可以是设计成减小流过存储器件的最大电流的两端结构。还提供了一种用于制造这种存储器件的方法。该方法包括沉积电阻器结构并沉积存储器件的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联设置以限制存储器件的开关电流。电阻器结构的结合对于获得满足各种类型的存储器件的开关规范的期望的器件开关电流水平是非常有用的。存储器件可以形成为可用于各种电子器件的大容量非易失性存储器集成电路的一部分。

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