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31. 发明授权

US08689017B2 Server power manager and method for dynamically managing server power consumption 有权
标题翻译：服务器电源管理器和动态管理服务器功耗的方法
公开(公告)号：US08689017B2
公开(公告)日：2014-04-01
申请号：US12634367
申请日：2009-12-09
申请人： Satyanarayana Nishtala
发明人： Satyanarayana Nishtala
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F12/06 , G06F12/08
摘要： A server power manager and method for dynamic server power management are generally described herein. The server power manager is configured to implement one or more server management policies that identify target server power consumption and/or target functionality for the server system. The server power manager determines an amount of excess processing capability and/or an amount of excess physical memory based on the target server power consumption and the target functionality. The server power manager may transition a processor core to a lower-operational state when at least a predetermined amount of excess processing capability is determined while maintaining server system functionality. The server power manager may transition a memory module to a lower-operational state when at least a predetermined amount of excess physical memory is determined while maintaining the server system functionality.
摘要翻译：本文一般地描述用于动态服务器电源管理的服务器电源管理器和方法。服务器电源管理器被配置为实现识别服务器系统的目标服务器功耗和/或目标功能的一个或多个服务器管理策略。服务器电源管理器基于目标服务器功耗和目标功能来确定多余的处理能力和/或多余的物理存储器量。当在保持服务器系统功能的同时确定至少预定量的多余处理能力时，服务器功率管理器可以将处理器核心转换到较低操作状态。当在保持服务器系统功能的同时确定至少预定量的多余的物理存储器时，服务器电源管理器可以将存储器模块转换到较低的操作状态。

32. 发明申请

US20120303993A1 METHOD AND APPARATUS FOR IMPROVED POWER EFFICIENCY FOR SERVER PLATFORMS 有权
标题翻译：用于服务器平台改进功率效率的方法和装置
公开(公告)号：US20120303993A1
公开(公告)日：2012-11-29
申请号：US13116345
申请日：2011-05-26
申请人： Satyanarayana Nishtala , Mark Ramon Imbertson
发明人： Satyanarayana Nishtala , Mark Ramon Imbertson
IPC分类号： G06F1/28
CPC分类号： G06F1/28 , G06F1/3206 , G06F1/3287 , Y02D10/171
摘要： In one embodiment, a method includes determining if a power load requirement associated with a server arrangement is below a threshold. The server arrangement includes at least a first power supply and a second power supply, as well as a capacitor arrangement. The method also includes providing power to the server arrangement using the first power supply and not the second power supply when it is determined that the power load requirement is below the threshold, and providing the power to the server arrangement using the first power supply and the second power supply when it is determined that the power load requirement is not below the threshold.
摘要翻译：在一个实施例中，一种方法包括确定与服务器装置相关联的功率负载要求是否低于阈值。服务器装置至少包括第一电源和第二电源以及电容器装置。该方法还包括当确定电力负载要求低于阈值时使用第一电源而不是第二电源向服务器装置提供电力，并且使用第一电源向服务器装置提供电力，并且当确定电力负载要求不低于阈值时，第二电源。

33. 发明授权

US07219169B2 Composite DMA disk controller for efficient hardware-assisted data transfer operations 有权
标题翻译：复合DMA磁盘控制器，用于高效的硬件辅助数据传输操作
公开(公告)号：US07219169B2
公开(公告)日：2007-05-15
申请号：US10261799
申请日：2002-09-30
申请人： Whay Sing Lee , Raghavendra Rao , Satyanarayana Nishtala
发明人： Whay Sing Lee , Raghavendra Rao , Satyanarayana Nishtala
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F3/0659 , G06F3/0626 , G06F3/0689 , G06F13/28
摘要： In one embodiment, a direct memory access (DMA) disk controller used in hardware-assisted data transfer operations includes command receiving logic to receive a data transfer command issued by a processor. The data transfer command identifies one or more locations in memory and multiple distinct regions on one or more disks accessible to the DMA disk controller. The DMA disk controller further includes data manipulation logic to transfer data between the memory locations and the distinct regions on the disks according to the data transfer command.
摘要翻译：在一个实施例中，用于硬件辅助数据传输操作的直接存储器访问（DMA）盘控制器包括用于接收由处理器发出的数据传送命令的命令接收逻辑。数据传输命令识别存储器中的一个或多个位置以及DMA磁盘控制器可访问的一个或多个磁盘上的多个不同区域。 DMA磁盘控制器还包括根据数据传输命令在存储器位置和磁盘上的不同区域之间传送数据的数据操纵逻辑。

34. 发明授权

US06381664B1 System for multisized bus coupling in a packet-switched computer system 有权
标题翻译：在分组交换计算机系统中用于多尺寸总线耦合的系统
公开(公告)号：US06381664B1
公开(公告)日：2002-04-30
申请号：US09597963
申请日：2000-06-20
申请人： Satyanarayana Nishtala , William C. Van Loo , Zahir Ebrahim
发明人： Satyanarayana Nishtala , William C. Van Loo , Zahir Ebrahim
IPC分类号： G06F1300
CPC分类号： G06F13/4018
摘要： A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width. In an alternative embodiment, the data transfer control system transfers the data words at substantially the full rate available, given the computer system's processor or clock speed and the width of the master bus, and the words are buffered before transference to the second bus. The speed of transference to the buffer is then not limited by the size of the second bus, but only by the size of the buffer, which preferably has an input bus at least as wide as that of the master bus. The system accommodates functional units of different sizes all to be couple to a master bus of a given size, where the different sizes may be larger or smaller than the master bus size, and accordingly the functional units can be built with optimal bus sizes for their particular functions without having to conform to a perhaps inappropriate, inefficient or expensive or wasteful master bus size.
摘要翻译：一种用于具有分组交换数据总线的计算机系统的数据传输控制系统，用于控制从具有一个总线宽度的设备到具有不同总线宽度的设备的数据字的传送。第一总线可以是主总线，第二总线是连接到计算机系统并耦合到主总线的诸如存储器或其他设备的功能单元的总线。当第二总线小于第一总线时，数据传输控制系统通过仅将每个时钟周期的部分字传送到第二总线来适应这种情况，有效延迟数据传输到第二总线可以处理的速率。传输速率因子基本上等于第二总线宽度与第一总线宽度的比率。在替代实施例中，数据传输控制系统以给定计算机系统的处理器或时钟速度和主总线的宽度的基本上可利用的全速率传送数据字，并且在传送到第二总线之前缓冲字。然后，传输到缓冲器的速度不受第二总线的大小限制，而仅由缓冲器的大小限制，缓冲器的大小优选地具有至少与母线总线相同的输入总线。该系统可容纳不同尺寸的功能单元，以连接到给定尺寸的主总线，其中不同尺寸可能大于或小于主总线尺寸，因此功能单元可以以最佳总线大小来构建特定功能，而不必符合可能不合适，低效或昂贵或浪费的主总线大小。

35. 发明授权

US5684977A Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system 失效
标题翻译：回写取消处理系统，用于分组交换高速缓存一致多处理器系统
公开(公告)号：US5684977A
公开(公告)日：1997-11-04
申请号：US415040
申请日：1995-03-31
申请人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
发明人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller. The system controller processes each memory transaction and maintains a set of duplicate cache tags (Dtags) for each data processor. Finally, the system controller contains transaction execution circuitry for activating a transaction for servicing by the interconnect. The transaction execution circuitry pipelines memory access requests from the data processors, and includes invalidation circuitry for processing each writeback request from a given data processor prior to activation to determine if the Dtag index corresponding to the victimized cache line is invalid. Thereafter, the invalidation circuitry activates writeback requests only if the Dtag index is not invalid and cancels the writeback request if the Dtag index is invalid.
摘要翻译：提供了具有多个子系统和耦合到系统控制器的主存储器的多处理器计算机系统。互连模块根据从系统控制器接收的互连控制信号，互连主存储器和子系统。至少两个子系统是数据处理器，每个数据处理器具有存储多个数据块的相应缓存存储器和一组主缓存标签（Etags），包括由高速缓存存储器存储的每个数据块的一个高速缓存标签。每个数据处理器包括用于向系统控制器发送存储器事务请求的主接口。系统控制器处理每个存储器事务，并为每个数据处理器维护一组重复的缓存标签（Dtags）。最后，系统控制器包含用于激活交易以进行互连维修的事务执行电路。交易执行电路管理来自数据处理器的存储器访问请求，并且包括用于在激活之前处理来自给定数据处理器的每个回写请求的无效电路，以确定与受害高速缓存行对应的Dtag索引是否无效。此后，无效电路仅在Dtag索引无效时才激活写回请求，如果Dtag索引无效则取消写回请求。

36. 发明授权

US5644753A Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system 失效
标题翻译：快速，双端口缓存控制器，用于数据包交换缓存一致多处理器系统中的数据处理器
公开(公告)号：US5644753A
公开(公告)日：1997-07-01
申请号：US714965
申请日：1996-09-17
申请人： Zahir Ebrahim , Kevin Normoyle , Satyanarayana Nishtala , William C. Van Loo
发明人： Zahir Ebrahim , Kevin Normoyle , Satyanarayana Nishtala , William C. Van Loo
IPC分类号： G11C11/41 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0815 , G06F12/0804 , G06F12/0817 , G06F12/0833
摘要： A multiprocessor computer system has data processors and a main memory coupled to a system controller. Each data processor has a cache memory. Each cache memory has a cache controller with two ports for receiving access requests. A first port receives access requests from the associated data processor and a second port receives access requests from the system controller. All cache memory access requests include an address value; access requests from the system controller also include a mode flag. A comparator in the cache controller processes the address value in each access request and generates a hit/miss signal indicating whether the data block corresponding to the address value is stored in the cache memory. The cache controller has two modes of operation, including a first standard mode of operation in which read/write access to the cache memory is preceded by generation of the hit/miss signal by the comparator, and a second accelerated mode of operation in which read/write access to the cache memory is initiated without waiting for the comparator to process the access request's address value. The first mode of operation is used for all access requests by the data processor and for system controller access requests when the mode flag has a first value. The second mode of operation is used for the system controller access requests when the mode flag has a second value distinct from the first value.
摘要翻译：多处理器计算机系统具有耦合到系统控制器的数据处理器和主存储器。每个数据处理器都有一个缓存存储器。每个高速缓冲存储器具有一个具有两个用于接收访问请求的端口的缓存控制器。第一端口从相关联的数据处理器接收访问请求，第二端口从系统控制器接收访问请求。所有高速缓存存储器访问请求都包含一个地址值; 来自系统控制器的访问请求还包括模式标志。高速缓存控制器中的比较器处理每个访问请求中的地址值，并产生指示与地址值相对应的数据块是否存储在高速缓冲存储器中的命中/未命中信号。高速缓存控制器具有两种操作模式，包括第一标准操作模式，其中先前通过比较器生成命中/未命中信号，其中对高速缓冲存储器的读/写访问以及其中读取的第二加速操作模式启动对高速缓冲存储器的写入访问，而不必等待比较器处理访问请求的地址值。当模式标志具有第一个值时，第一种操作模式用于数据处理器和系统控制器访问请求的所有访问请求。当模式标志具有与第一值不同的第二值时，第二操作模式用于系统控制器访问请求。

37. 发明申请

US20090177861A1 SYSTEM AND METHODS FOR MEMORY EXPANSION 有权
标题翻译：用于存储扩展的系统和方法
公开(公告)号：US20090177861A1
公开(公告)日：2009-07-09
申请号：US11971080
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Dmitry Barsky
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Dmitry Barsky
IPC分类号： G06F9/34
CPC分类号： G06F13/4243 , G11C5/04
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括从物理双列直插式存储器模块（DIMM）接收第一初始化数据，并将第一初始化数据转换为映射到物理DIMM的逻辑DIMM的第二初始化数据。该示例性实施例还可以包括基于第二初始化数据来编程存储器控制器。

38. 发明授权

US07114014B2 Method and system for data movement in data storage systems employing parcel-based data mapping 有权
标题翻译：采用基于数据映射的数据存储系统中数据移动的方法和系统
公开(公告)号：US07114014B2
公开(公告)日：2006-09-26
申请号：US10607770
申请日：2003-06-27
申请人： Michael Yatziv , Satyanarayana Nishtala , Whay Sing Lee , Raghavendra J. Rao
发明人： Michael Yatziv , Satyanarayana Nishtala , Whay Sing Lee , Raghavendra J. Rao
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Embodiments of the present invention provide methods and systems for data movement in data storage systems. For one embodiment, a physical data storage parcel containing a first type of data requiring a first type of processing and a second type of data requiring a second type of processing is created. The first type of data is transferred to a first memory address space via a direct memory access operation and the second type of data is transferred to a second memory address space via the direct memory access operation. For one embodiment, the first type of data and the second type of data are copied to physically distinct data storage mediums. In an alternative embodiment, the first type of data and the second type of data are copied to distinct data storage structures of the same device. Thus, the bulk memory access operations are performed via hardware, thereby reducing performance impact.
摘要翻译：本发明的实施例提供了数据存储系统中数据移动的方法和系统。对于一个实施例，创建包含需要第一类型处理的第一类型数据和需要第二类型处理的第二类型数据的物理数据存储包。第一类型的数据经由直接存储器访问操作被传送到第一存储器地址空间，并且第二类型的数据经由直接存储器访问操作被传送到第二存储器地址空间。对于一个实施例，将第一类型的数据和第二类型的数据复制到物理上不同的数据存储介质。在替代实施例中，将第一类型的数据和第二类型的数据复制到同一设备的不同数据存储结构。因此，大容量存储器访问操作通过硬件执行，从而降低性能影响。

39. 发明授权

US6141741A Computer system with a shared address bus and pipelined write operations 失效
标题翻译：具有共享地址总线和流水线写入操作的计算机系统
公开(公告)号：US6141741A
公开(公告)日：2000-10-31
申请号：US705057
申请日：1996-08-29
申请人： Curtis Priem , Satyanarayana Nishtala , Michael G. Lavelle , Thomas Webber , Daniel E. Lenoski , Peter A. Mehring , Guy Moffat , Christopher R. Owen
发明人： Curtis Priem , Satyanarayana Nishtala , Michael G. Lavelle , Thomas Webber , Daniel E. Lenoski , Peter A. Mehring , Guy Moffat , Christopher R. Owen
IPC分类号： G06F12/02 , G06F13/16 , G06F13/36 , G06F13/42 , G06F12/00
CPC分类号： G06F12/0215 , G06F13/161 , G06F13/1615
摘要： A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes. This overlapping operation allows the bus to be completely utilized during write operations, thereby improving data bandwidth.
摘要翻译：描述了由系统存储器和从设备共享的具有多路复用地址总线的计算机系统。通过提供总线控制器来在多路复用地址总线上执行两周期地址序列，将从设备并入现有系统存储器配置。地址序列之后是数据传输。在接收地址信息的时间和接收与地址信息对应的数据的时间之间可以存在随机延迟。这个随机延迟可以被系统CPU用于其他计算目的。在接收到第一个数据写入的确认之前，系统的总线控制器在总线上执行多个或流水线的数据写入。在该方案中，通常在接收后续数据写入的相同时间段期间发送对第一数据写入的确认。因此，数据传输确认与数据写入重叠。这种重叠操作允许在写入操作期间完全利用总线，从而提高数据带宽。

40. 发明授权

US6064672A System for dynamic ordering support in a ringlet serial interconnect 失效
公开(公告)号：US6064672A
公开(公告)日：2000-05-16
申请号：US674033
申请日：1996-07-01
申请人： William C. Van Loo , Satyanarayana Nishtala
发明人： William C. Van Loo , Satyanarayana Nishtala
IPC分类号： H04L1/18 , H04L12/40 , H04L12/42 , H04L12/64 , H04L29/06 , H04J3/24
CPC分类号： H04L12/42 , H04L1/1806 , H04L12/40052 , H04L12/40091 , H04L1/1809
摘要： A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets. Strong ordering is thus supported, since the sending order of packets can be maintained for processing due to the resends, and nonidempotent commands are supported due to the consumer nodes' ability to determine whether they have already processed a given packet, and to send an acknowledge-done reply if that is the case.

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