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1. 发明授权

US4292995A Locking valve apparatus 失效
标题翻译：锁止阀装置
公开(公告)号：US4292995A
公开(公告)日：1981-10-06
申请号：US121028
申请日：1980-02-13
申请人： Mario Mazzola
发明人： Mario Mazzola
IPC分类号： F16K35/06
CPC分类号： F16K35/06 , Y10T137/7131 , Y10T70/7876
摘要： The locking valve apparatus includes a valve housing containing a rotatable cylinder lock with a keyway extending into the cylinder from one end and with a stationary cylindrical member of the valve housing encircling this rotatable cylinder. An alignment element on the outside of this stationary cylindrical member is adapted to position, align and guide a removable handle for the valve. This removable handle includes a sleeve defining a socket which is adapted to nest over the stationary cylindrical member of the valve housing when the handle is engaged for operating the valve. A key is located inside of this sleeve socket, being adjustably secured therein, and the socket is provided with a slot, which the user of the handle must align with the alignment element, otherwise the handle cannot be positioned on the valve housing. Accordingly, when the handle socket is placed on the valve housing with the slot being slid over the alignment element, the key becomes properly positioned for entry into the keyway and the handle becomes properly positioned for operating the locking valve mechanism. Furthermore, the interior end of this slot connects with a second arcuate slot adapted to receive the alignment element for permitting the handle to be turned relative to the valve housing only when the socket has been fully seated, thereby protecting the key itself from being twisted until is has been fully inserted into the keyway.
摘要翻译：锁定阀装置包括阀壳体，该阀壳体包含可旋转的气缸锁，其具有从一端延伸到气缸中的键槽以及围绕该可旋转气缸的阀壳体的固定圆柱形构件。在该固定圆柱形构件的外侧上的对准元件适于定位，对准和引导用于阀的可拆卸手柄。该可移除手柄包括限定了插座的套筒，当套管接合以操作阀门时，套筒适于嵌套在阀壳体的固定圆柱形构件上。钥匙位于该套筒的内部，可调节地固定在其中，并且插座设置有槽，使用者的手柄必须与对准元件对准，否则手柄不能定位在阀壳体上。因此，当手柄插座被放置在阀壳体上，其中狭槽在对准元件上滑动时，钥匙被适当地定位以进入键槽，并且手柄被适当地定位以操作锁定阀机构。此外，该槽的内端与适于容纳对准元件的第二弧形槽连接，仅当套筒完全就位时才允许手柄相对于阀壳转动，从而保护钥匙本身不被扭曲，直到已经完全插入键槽。

2. 发明授权

US08825965B2 System and methods for memory expansion 有权
标题翻译：用于内存扩展的系统和方法
公开(公告)号：US08825965B2
公开(公告)日：2014-09-02
申请号：US11971066
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00 , G06F13/42 , G06F13/16 , G06F12/02 , G06F12/06
CPC分类号： G06F12/1009 , G06F11/1016 , G06F12/0207 , G06F12/0292 , G06F12/0607 , G06F13/1684 , G06F13/4234
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括通过信道从存储器控制器接收存储器请求。基于存储器请求，示例性实施例包括选择存储器中的位置以耦合到信道的子信道并且配置该场效应晶体管集合以将该信道与子信道耦合。在示例实施例中，可以允许数据通过信道和子信道在存储器控制器和存储器中的位置之间流动。

3. 发明授权

US08621132B2 System and methods for memory expansion 有权
标题翻译：用于内存扩展的系统和方法
公开(公告)号：US08621132B2
公开(公告)日：2013-12-31
申请号：US11971080
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Dmitry Barsky
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Dmitry Barsky
IPC分类号： G06F12/00
CPC分类号： G06F13/4243 , G11C5/04
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括从物理双列直插式存储器模块（DIMM）接收第一初始化数据，并将第一初始化数据转换为映射到物理DIMM的逻辑DIMM的第二初始化数据。该示例性实施例还可以包括基于第二初始化数据来编程存储器控制器。

4. 发明授权

US4151565A Discrimination during reading of data prerecorded in different codes 失效
标题翻译：阅读不同规则预录的数据时的歧视
公开(公告)号：US4151565A
公开(公告)日：1979-04-24
申请号：US794513
申请日：1977-05-06
申请人： Mario Mazzola
发明人： Mario Mazzola
IPC分类号： H03M5/00 , G11B20/14 , H03K9/06 , H03M5/12 , H04L25/49 , G11B5/09 , G11B27/10
CPC分类号： G11B20/1423 , G11B20/1419
摘要： A circuit for the decoding during reading of data prerecorded on a magnetic medium comprising a circuit for recognition of the recording code of the data recorded on the support by the recognition of the frequency of an input signal generated during the reading of the support and a frequency generating circuit controlled by the recognition circuit for generating a signal of predetermined frequency for the conversion of the recording code recognized into a binary code. A read-only memory comprising two zones is responsive to the recognition means for generating correcting words applied to a counter for controlling the position of a decoding window generated by a phase locked loop oscillator.
摘要翻译：一种用于在读取在磁介质上预录的数据进行解码的电路，包括用于通过识别读取支持期间产生的输入信号的频率来识别记录在支持体上的数据的记录码的电路，由识别电路控制的生成电路，用于产生用于将识别为二进制码的记录码的转换的预定频率的信号。包括两个区域的只读存储器响应于识别装置，用于产生应用于计数器的校正字，以控制由锁相环振荡器产生的解码窗口的位置。

5. 发明授权

US08407394B2 System and methods for memory expansion 有权
标题翻译：用于内存扩展的系统和方法
公开(公告)号：US08407394B2
公开(公告)日：2013-03-26
申请号：US11971091
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00
CPC分类号： G06F12/0292 , G06F12/06
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括检测针对映射到逻辑秩的逻辑rand和多个物理等级的存储器命令。该示例性实施例还可以包括基于确定存储器命令将被发布到物理等级的数量而将存储器命令发布到物理队列的数量。

6. 发明申请

US20090177853A1 SYSTEM AND METHODS FOR MEMORY EXPANSION 有权
标题翻译：用于存储扩展的系统和方法
公开(公告)号：US20090177853A1
公开(公告)日：2009-07-09
申请号：US11971091
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00
CPC分类号： G06F12/0292 , G06F12/06
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括检测针对映射到逻辑秩的逻辑rand和多个物理等级的存储器命令。该示例性实施例还可以包括基于确定存储器命令将被发布到物理等级的数量而将存储器命令发布到物理队列的数量。

7. 发明授权

US5392513A Steampath and process of retrofitting a nozzle thereof 失效
标题翻译：电动车及其喷嘴的加工过程
公开(公告)号：US5392513A
公开(公告)日：1995-02-28
申请号：US171032
申请日：1993-12-21
申请人： Mario Mazzola , Michael T. Hamlin , Richard I. Cromer , John Costantini
发明人： Mario Mazzola , Michael T. Hamlin , Richard I. Cromer , John Costantini
IPC分类号： B23P6/00 , F01D9/04 , B23P19/04
CPC分类号： B23P6/005 , F01D9/047 , F05D2230/80 , Y10T29/49318 , Y10T29/49323 , Y10T29/49737
摘要： A process for replacing a multi-piece steampath in a nozzle box (12) where, initially, the steampath (22) is secured between upper (24) and lower (26) ring components by means of axially accessible, arcuate welds (36, 38) includes the steps of:a) axially machining the arcuate welds (36, 38) so as to permit removal of the steampath (22) in a direction axially away from the nozzle box;b) further machining a forward portion of the lower ring component to provide a substantially vertical weld surface; andc) securing a one-piece steampath (222) in place by an axially accessible upper weld (236) and a radially accessible lower weld (238).A nozzle box (212) for a steam turbine includes a torus portion 218 and a bridge ring portion (220), the bridge ring portion including radially inner and outer bridge rings (226, 224) connected by a plurality of bridge elements (234); a one-piece steampath (222) secured between the radially inner and outer bridge rings (226,224), the steampath (222) having integral upper and lower bands (232, 230) connected by integral steampath partitions (234), the steampath being secured to the upper ring (224) by an axially accessible weld (236) and to the lower bridge ring (226) by a radially accessible weld (238).
摘要翻译：一种用于更换喷嘴箱（12）中的多件式汽车的方法，其中最初通过轴向可接近的弓形焊缝（36）将汽车（22）固定在上部（24）和下部（26）环部件之间， 38）包括以下步骤：a）轴向加工弓形焊缝（36,38），以允许沿轴向远离喷嘴箱的方向移除汽车（22）; b）进一步加工下环部件的前部以提供基本垂直的焊接表面; 以及c）通过轴向可接近的上焊缝（236）和径向可接近的下焊缝（238）将一件式的车辆（222）固定就位。一种用于蒸汽涡轮机的喷嘴箱（212）包括环面部分218和桥环部分（220），所述桥环部分包括由多个桥接元件（234）连接的径向内外桥环（226,224） ; 固定在所述径向内和外桥环（226,224）之间的单件式车床（222），所述车辆（222）具有通过整体式汽车隔板（234）连接的整体上下带（232,230），所述车轮被固定通过轴向可接近的焊接（236）到达上环（224），并通过可径向接触的焊接（238）连接到下桥环（226）。

8. 发明申请

US20090177849A1 SYSTEM AND METHODS FOR MEMORY EXPANSION 有权
标题翻译：用于存储扩展的系统和方法
公开(公告)号：US20090177849A1
公开(公告)日：2009-07-09
申请号：US11971066
申请日：2008-01-08
申请人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
发明人： Mario Mazzola , Satyanarayana Nishtala , Luca Cafiero , Philip Manela
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F11/1016 , G06F12/0207 , G06F12/0292 , G06F12/0607 , G06F13/1684 , G06F13/4234
摘要： This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
摘要翻译：本文档还讨论了一个用于内存扩展的示例系统和方法。示例实施例包括通过信道从存储器控制器接收存储器请求。基于存储器请求，示例性实施例包括选择存储器中的位置以耦合到信道的子信道并且配置该场效应晶体管集合以将该信道与子信道耦合。在示例实施例中，可以允许数据通过信道和子信道在存储器控制器和存储器中的位置之间流动。

9. 发明授权

US5796732A Architecture for an expandable transaction-based switching bus 失效
标题翻译：基于可扩展事务的交换总线架构
公开(公告)号：US5796732A
公开(公告)日：1998-08-18
申请号：US621720
申请日：1996-03-28
申请人： Mario Mazzola , Tom Edsall , Massimo Prati , Luca Cafiero
发明人： Mario Mazzola , Tom Edsall , Massimo Prati , Luca Cafiero
IPC分类号： H04L12/56 , H04L12/403
CPC分类号： H04L49/102 , H04L49/205 , H04L49/254 , H04L49/30 , H04L49/351
摘要： A switching bus architecture enables efficient transfer of data within a network switch having a plurality of ports interconnected by a high-performance switching bus. The architecture is preferably implemented as novel port interface and forwarding engine circuitry that cooperate to efficiently transmit data to, and receive data from, the switching bus in accordance with a 2-tier arbitration policy that ensures adequate port access to the bus. As a result of such a cooperating arrangement, the architecture improves the transfer efficiency of the switch by providing all ports sufficient bus access to convey accurate data throughout the switch.
摘要翻译：交换总线架构能够在具有通过高性能交换总线互连的多个端口的网络交换机内进行有效的数据传输。该架构优选地被实现为新颖的端口接口和转发引擎电路，其协作以根据确保对总线的足够端口访问的2级仲裁策略来有效地向交换总线传输数据和从交换总线接收数据。作为这种协作安排的结果，该架构通过提供足够的总线访问来提供交换机的传输效率，从而在整个交换机中传送准确的数据。

10. 发明授权

US5280500A Method and apparatus for multilevel encoding for a local area network 失效
标题翻译：用于局域网多级编码的方法和装置
公开(公告)号：US5280500A
公开(公告)日：1994-01-18
申请号：US775641
申请日：1991-10-10
申请人： Mario Mazzola , Luca Cafiero , Maurilio DeNicolo
发明人： Mario Mazzola , Luca Cafiero , Maurilio DeNicolo
IPC分类号： H03M5/18 , H03M5/20 , H04L25/49
CPC分类号： H04L25/4917 , H03M5/18 , H03M5/20
摘要： A multilevel encoding scheme for transmitted data that encodes data in a multilevel code wherein the amplitude of any transition is always exactly one level during any time interval. A single-level transition between any two adjacent levels during a time interval represents a logical "1"; no transition during a time interval represents a logical "0". In a specific embodiment, modulation is limited to three defined amplitude levels equally space in amplitude and encoding is according to a three-level code. A four-bit to five-bit encoding scheme may be used to distribute bits for minimizing d.c. offset. The input data is preferably further scrambled to minimize aberrations in the emissions spectrum of signal carried over unshielded media.
摘要翻译：用于对多级代码中的数据进行编码的传输数据的多级编码方案，其中在任何时间间隔期间任何转换的幅度总是正好为一级。在一段时间间隔内任何两个相邻级别之间的单级转换代表逻辑“1”; 在时间间隔期间没有转换代表逻辑“0”。在一个具体实施例中，调制被限制在三个定义的振幅水平上，幅度上相等的空间，并且根据三电平码进行编码。可以使用四位到五位编码方案来分配比特以最小化直流。抵消。输入数据优选进一步加扰以最小化在非屏蔽介质上携带的信号的发射光谱中的像差。

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